Re: [Xen-devel] [PATCH RFC v1 02/74] x86: Common cpuid faulting support

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 04.01.18 at 14:05, <wei.liu2@xxxxxxxxxx> wrote:
> @@ -518,7 +522,7 @@ static void early_init_amd(struct cpuinfo_x86 *c)
>       if (c == &boot_cpu_data)
>               amd_init_levelling();
>  
> -     amd_ctxt_switch_levelling(NULL);
> +     ctxt_switch_levelling(NULL);
>  }

I don't really understand this change: Why don't you call
amd_ctxt_switch_masking() instead? ctxt_switch_levelling(NULL)
doesn't do anything else (assuming the call here is wrapped by a
"if (!cpu_has_cpuid_faulting)"). Same for the Intel variant then.

> +static void set_cpuid_faulting(bool enable)
> +{
> +     uint64_t *this_misc_features = &this_cpu(msr_misc_features);
> +     uint64_t val = *this_misc_features;
> +
> +     if (!!(val & MSR_MISC_FEATURES_CPUID_FAULTING) == enable)
> +             return;
> +
> +     val ^= MSR_MISC_FEATURES_CPUID_FAULTING;
> +
> +     wrmsrl(MSR_INTEL_MISC_FEATURES_ENABLES, val);
> +     *this_misc_features = val;

If you maintain a cache for the full MSR, then I think you'd better
create wrappers to do reads and writes, just like we have for
EFER.

Jan


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