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[Xen-devel] [PATCH 1/6] x86: move invocations of hvm_flush_guest_tlbs()

Their need is not tied to the actual flushing of TLBs, but the ticking
of the TLB clock. Make this more obvious by folding the two invocations
into a single one in pre_flush().

Also defer the latching of CR4 in write_cr3() until after pre_flush()
(and hence implicitly until after IRQs are off), making operation
sequence the same in both cases (eliminating the theoretical risk of
pre_flush() altering CR4). This then also improves register allocation,
as the compiler doesn't need to use a callee-saved register for "cr4"

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/xen/arch/x86/flushtlb.c
+++ b/xen/arch/x86/flushtlb.c
@@ -49,6 +49,8 @@ static u32 pre_flush(void)
+    hvm_flush_guest_tlbs();
     return t2;
@@ -71,15 +73,14 @@ static void post_flush(u32 t)
 void write_cr3(unsigned long cr3)
-    unsigned long flags, cr4 = read_cr4();
+    unsigned long flags, cr4;
     u32 t;
     /* This non-reentrant function is sometimes called in interrupt context. */
     t = pre_flush();
-    hvm_flush_guest_tlbs();
+    cr4 = read_cr4();
     write_cr4(cr4 & ~X86_CR4_PGE);
     asm volatile ( "mov %0, %%cr3" : : "r" (cr3) : "memory" );
@@ -121,8 +122,6 @@ unsigned int flush_area_local(const void
             u32 t = pre_flush();
             unsigned long cr4 = read_cr4();
-            hvm_flush_guest_tlbs();
             write_cr4(cr4 & ~X86_CR4_PGE);

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