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Re: [Xen-devel] [PATCH v2 06/27] x86/entry/64: Adapt assembly for PIE support
- To: Christoph Lameter <cl@xxxxxxxxx>
- From: Thomas Garnier <thgarnie@xxxxxxxxxx>
- Date: Wed, 14 Mar 2018 17:09:37 +0000
- Cc: Kate Stewart <kstewart@xxxxxxxxxxxxxxxxxxx>, Nicolas Pitre <nicolas.pitre@xxxxxxxxxx>, Michal Hocko <mhocko@xxxxxxxx>, Sergey Senozhatsky <sergey.senozhatsky.work@xxxxxxxxx>, Petr Mladek <pmladek@xxxxxxxx>, Len Brown <len.brown@xxxxxxxxx>, Peter Zijlstra <peterz@xxxxxxxxxxxxx>, Christopher Li <sparse@xxxxxxxxxxx>, Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx>, the arch/x86 maintainers <x86@xxxxxxxxxx>, Dominik Brodowski <linux@xxxxxxxxxxxxxxxxxxxx>, LKML <linux-kernel@xxxxxxxxxxxxxxx>, Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx>, Pavel Machek <pavel@xxxxxx>, "H . Peter Anvin" <hpa@xxxxxxxxx>, Kernel Hardening <kernel-hardening@xxxxxxxxxxxxxxxxxx>, Jiri Slaby <jslaby@xxxxxxx>, Alok Kataria <akataria@xxxxxxxxxx>, Linux Doc Mailing List <linux-doc@xxxxxxxxxxxxxxx>, linux-arch <linux-arch@xxxxxxxxxxxxxxx>, Herbert Xu <herbert@xxxxxxxxxxxxxxxxxxx>, Baoquan He <bhe@xxxxxxxxxx>, Jonathan Corbet <corbet@xxxxxxx>, Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>, Radim Krčmář <rkrcmar@xxxxxxxxxx>, Kyle Huey <me@xxxxxxxxxxxx>, Ingo Molnar <mingo@xxxxxxxxxx>, xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Sparse Mailing-list <linux-sparse@xxxxxxxxxxxxxxx>, Matthias Kaehlcke <mka@xxxxxxxxxxxx>, Andrey Ryabinin <aryabinin@xxxxxxxxxxxxx>, Borislav Petkov <bp@xxxxxxx>, virtualization@xxxxxxxxxxxxxxxxxxxxxxxxxx, Alexey Dobriyan <adobriyan@xxxxxxxxx>, Matthew Wilcox <mawilcox@xxxxxxxxxxxxx>, Linux Crypto Mailing List <linux-crypto@xxxxxxxxxxxxxxx>, kvm list <kvm@xxxxxxxxxxxxxxx>, Tom Lendacky <thomas.lendacky@xxxxxxx>, Rik van Riel <riel@xxxxxxxxxx>, Jan H . Schönherr <jschoenh@xxxxxxxxx>, Kees Cook <keescook@xxxxxxxxxxxx>, Arnd Bergmann <arnd@xxxxxxxx>, Dou Liyang <douly.fnst@xxxxxxxxxxxxxx>, Daniel Micay <danielmicay@xxxxxxxxx>, "H . J . Lu" <hjl.tools@xxxxxxxxx>, Steven Rostedt <rostedt@xxxxxxxxxxx>, Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>, Dennis Zhou <dennisszhou@xxxxxxxxx>, Jason Baron <jbaron@xxxxxxxxxx>, Borislav Petkov <bp@xxxxxxxxx>, Nicholas Piggin <npiggin@xxxxxxxxx>, Andy Lutomirski <luto@xxxxxxxxxx>, Josh Poimboeuf <jpoimboe@xxxxxxxxxx>, Thomas Gleixner <tglx@xxxxxxxxxxxxx>, Ashish Kalra <ashish@xxxxxxxxxxxxxx>, Ingo Molnar <mingo@xxxxxxxxxx>, Juergen Gross <jgross@xxxxxxxx>, Kyle McMartin <kyle@xxxxxxxxxx>, "Paul E . McKenney" <paulmck@xxxxxxxxxxxxxxxxxx>, Greg KH <gregkh@xxxxxxxxxxxxxxxxxxx>, Linux PM list <linux-pm@xxxxxxxxxxxxxxx>, Randy Dunlap <rdunlap@xxxxxxxxxxxxx>, "Rafael J. Wysocki" <rjw@xxxxxxxxxxxxx>, Cao jin <caoj.fnst@xxxxxxxxxxxxxx>, Jia Zhang <qianyue.zj@xxxxxxxxxxxxxxx>, "Luis R . Rodriguez" <mcgrof@xxxxxxxxxx>, Lukas Wunner <lukas@xxxxxxxxx>, David Woodhouse <dwmw@xxxxxxxxxxxx>, Rob Landley <rob@xxxxxxxxxxx>, Philippe Ombredanne <pombredanne@xxxxxxxx>, Tejun Heo <tj@xxxxxxxxxx>, Paolo Bonzini <pbonzini@xxxxxxxxxx>, Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx>, "David S . Miller" <davem@xxxxxxxxxxxxx>, "Kirill A. Shutemov" <kirill.shutemov@xxxxxxxxxxxxxxx>, Joerg Roedel <joro@xxxxxxxxxx>
- Delivery-date: Wed, 14 Mar 2018 17:10:00 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On Wed, Mar 14, 2018 at 8:55 AM Christopher Lameter <cl@xxxxxxxxx> wrote:
> On Wed, 14 Mar 2018, Peter Zijlstra wrote:
> > On Tue, Mar 13, 2018 at 01:59:24PM -0700, Thomas Garnier wrote:
> > > @@ -1576,7 +1578,9 @@ first_nmi:
> > > addq $8, (%rsp) /* Fix up RSP */
> > > pushfq /* RFLAGS */
> > > pushq $__KERNEL_CS /* CS */
> > > - pushq $1f /* RIP */
> > > + pushq %rax /* Support Position Independent Code */
> > > + leaq 1f(%rip), %rax /* RIP */
> > > + xchgq %rax, (%rsp) /* Restore RAX, put 1f */
> > > iretq /* continues at repeat_nmi below */
> > > UNWIND_HINT_IRET_REGS
> > > 1:
> >
> > Urgh, xchg with a memop has an implicit LOCK prefix.
> this_cpu_xchg uses no lock cmpxchg as a replacement to reduce latency.
Great, I will update my implementation.
Thanks Peter and Christoph.
> From linux/arch/x86/include/asm/percpu.h
> /*
> * xchg is implemented using cmpxchg without a lock prefix. xchg is
> * expensive due to the implied lock prefix. The processor cannot
prefetch
> * cachelines if xchg is used.
> */
> #define percpu_xchg_op(var, nval) \
> ({ \
> typeof(var) pxo_ret__; \
> typeof(var) pxo_new__ = (nval); \
> switch (sizeof(var)) { \
> case 1: \
> asm("\n\tmov "__percpu_arg(1)",%%al" \
> "\n1:\tcmpxchgb %2, "__percpu_arg(1) \
> "\n\tjnz 1b" \
> : "=&a" (pxo_ret__), "+m" (var) \
> : "q" (pxo_new__) \
> : "memory"); \
> break; \
> case 2: \
> asm("\n\tmov "__percpu_arg(1)",%%ax" \
> "\n1:\tcmpxchgw %2, "__percpu_arg(1) \
> "\n\tjnz 1b" \
> : "=&a" (pxo_ret__), "+m" (var) \
> : "r" (pxo_new__) \
> : "memory"); \
> break; \
> case 4: \
> asm("\n\tmov "__percpu_arg(1)",%%eax" \
> "\n1:\tcmpxchgl %2, "__percpu_arg(1) \
> "\n\tjnz 1b" \
> : "=&a" (pxo_ret__), "+m" (var) \
> : "r" (pxo_new__) \
> : "memory"); \
> break; \
> case 8: \
> asm("\n\tmov "__percpu_arg(1)",%%rax" \
> "\n1:\tcmpxchgq %2, "__percpu_arg(1) \
> "\n\tjnz 1b" \
> : "=&a" (pxo_ret__), "+m" (var) \
> : "r" (pxo_new__) \
> : "memory"); \
> break; \
> default: __bad_percpu_size(); \
> } \
> pxo_ret__; \
--
Thomas
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