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Re: [Xen-devel] [PATCH v2 06/27] x86/entry/64: Adapt assembly for PIE support



On 14/03/2018 16:54, Christopher Lameter wrote:
>>> +   pushq   %rax            /* Support Position Independent Code */
>>> +   leaq    1f(%rip), %rax  /* RIP */
>>> +   xchgq   %rax, (%rsp)    /* Restore RAX, put 1f */
>>>     iretq                   /* continues at repeat_nmi below */
>>>     UNWIND_HINT_IRET_REGS
>>>  1:
>> Urgh, xchg with a memop has an implicit LOCK prefix.
> this_cpu_xchg uses no lock cmpxchg as a replacement to reduce latency.

That requires using a second register, since %rax is used as the
comparison source.  At this point it's easier to just push %rax twice:

        pushq %rax
        pushq %rax
        leaq 1f(%ip), %rax
        movq %rax, 8(%rsp)
        popq %rax
        iretq

Paolo

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