[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v1 14/15] arm64: vgic-v3: Add ICV_AP(0/1)Rn_EL1 handler
This patch is a xen port of linux commit f9e7449c780f688bf61a13dfa8c344afeb4ad6e0. Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1 registers. We just map them to the corresponding ICH_AP(0/1)Rn_EL2 registers. Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx> diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index 5af5142b21..2ca1145336 100644 --- a/xen/arch/arm/arm64/vgic-v3-sr.c +++ b/xen/arch/arm/arm64/vgic-v3-sr.c @@ -694,6 +694,66 @@ spurious: set_user_reg(regs, regidx, lr_val & ICH_LR_VIRTUAL_ID_MASK); } +static void __vgic_v3_read_apxrn(struct cpu_user_regs *regs, int regidx, + const union hsr hsr, int n) +{ + uint32_t val; + + if ( !__vgic_v3_get_group(hsr) ) + val = __vgic_v3_read_ap0rn(n); + else + val = __vgic_v3_read_ap1rn(n); + + set_user_reg(regs, regidx, val); +} + +static void __vgic_v3_write_apxrn(struct cpu_user_regs *regs, int regidx, + const union hsr hsr, int n) +{ + uint32_t val = get_user_reg(regs, regidx); + + if (!__vgic_v3_get_group(hsr)) + __vgic_v3_write_ap0rn(val, n); + else + __vgic_v3_write_ap1rn(val, n); +} + +void handle_apxr0(struct cpu_user_regs *regs, int regidx, + const union hsr hsr) +{ + if(hsr.sysreg.read) + __vgic_v3_read_apxrn(regs, regidx, hsr, 0); + else + __vgic_v3_write_apxrn(regs, regidx, hsr, 0); +} + +void handle_apxr1(struct cpu_user_regs *regs, int regidx, + const union hsr hsr) +{ + if(hsr.sysreg.read) + __vgic_v3_read_apxrn(regs, regidx, hsr, 1); + else + __vgic_v3_write_apxrn(regs, regidx, hsr, 1); +} + +void handle_apxr2(struct cpu_user_regs *regs, int regidx, + const union hsr hsr) +{ + if(hsr.sysreg.read) + __vgic_v3_read_apxrn(regs, regidx, hsr, 2); + else + __vgic_v3_write_apxrn(regs, regidx, hsr, 2); +} + +void handle_apxr3(struct cpu_user_regs *regs, int regidx, + const union hsr hsr) +{ + if(hsr.sysreg.read) + __vgic_v3_read_apxrn(regs, regidx, hsr, 3); + else + __vgic_v3_write_apxrn(regs, regidx, hsr, 3); +} + bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs, const union hsr hsr) { bool ret = true; @@ -740,6 +800,26 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs, const union hsr hsr handle_hppir1(regs, regidx, hsr); break; + case HSR_SYSREG_ICC_AP0Rn_EL1(0): + case HSR_SYSREG_ICC_AP1Rn_EL1(0): + handle_apxr0(regs, regidx, hsr); + break; + + case HSR_SYSREG_ICC_AP0Rn_EL1(1): + case HSR_SYSREG_ICC_AP1Rn_EL1(1): + handle_apxr1(regs, regidx, hsr); + break; + + case HSR_SYSREG_ICC_AP0Rn_EL1(2): + case HSR_SYSREG_ICC_AP1Rn_EL1(2): + handle_apxr2(regs, regidx, hsr); + break; + + case HSR_SYSREG_ICC_AP0Rn_EL1(3): + case HSR_SYSREG_ICC_AP1Rn_EL1(3): + handle_apxr3(regs, regidx, hsr); + break; + default: ret = false; break; diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h index 8d1bd12348..e446b5de1c 100644 --- a/xen/include/asm-arm/arm64/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -85,6 +85,17 @@ #define HSR_SYSREG_PMINTENCLR_EL1 HSR_SYSREG(3,0,c9,c14,2) #define HSR_SYSREG_MAIR_EL1 HSR_SYSREG(3,0,c10,c2,0) #define HSR_SYSREG_AMAIR_EL1 HSR_SYSREG(3,0,c10,c3,0) +#define HSR_SYSREG_ICC_AP0Rn_EL1(n) HSR_SYSREG(3,0,c12,c8,4|n) +#define HSR_SYSREG_ICC_AP0R0_EL1 HSR_SYSREG_ICC_AP0Rn_EL1(0) +#define HSR_SYSREG_ICC_AP0R1_EL1 HSR_SYSREG_ICC_AP0Rn_EL1(1) +#define HSR_SYSREG_ICC_AP0R2_EL1 HSR_SYSREG_ICC_AP0Rn_EL1(2) +#define HSR_SYSREG_ICC_AP0R3_EL1 HSR_SYSREG_ICC_AP0Rn_EL1(3) +#define HSR_SYSREG_ICC_AP1Rn_EL1(n) HSR_SYSREG(3,0,c12,c9, n) +#define HSR_SYSREG_ICC_AP1R0_EL1 HSR_SYSREG_ICC_AP1Rn_EL1(0) +#define HSR_SYSREG_ICC_AP1R1_EL1 HSR_SYSREG_ICC_AP1Rn_EL1(1) +#define HSR_SYSREG_ICC_AP1R2_EL1 HSR_SYSREG_ICC_AP1Rn_EL1(2) +#define HSR_SYSREG_ICC_AP1R3_EL1 HSR_SYSREG_ICC_AP1Rn_EL1(3) + #define HSR_SYSREG_ICC_SGI1R_EL1 HSR_SYSREG(3,0,c12,c11,5) #define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6) #define HSR_SYSREG_ICC_SGI0R_EL1 HSR_SYSREG(3,2,c12,c11,7) -- 2.14.1 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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