[Xen-devel] [PATCH v1 15/15] Enable Group0/1 Traps by default for Cavium ThunderX1

[Manish Jaggi <manish.jaggi@xxxxxxxxxx>]

Enable trapping for Group0/1 register access when
CONFIG_CAVIUM_ERRATUM_30115 is enabled.

Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx>

diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 473e26111f..6ffed6a634 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -43,6 +43,7 @@
 #include <asm/gic.h>
 #include <asm/gic_v3_defs.h>
 #include <asm/gic_v3_its.h>
+#include <asm/cpuerrata.h>
 #include <asm/cpufeature.h>
 #include <asm/acpi.h>
 
@@ -825,7 +826,7 @@ static void gicv3_cpu_disable(void)
 
 static void gicv3_hyp_init(void)
 {
-    uint32_t vtr;
+    uint32_t vtr, hcr = GICH_HCR_EN;
 
     vtr = READ_SYSREG32(ICH_VTR_EL2);
     gicv3_info.nr_lrs  = (vtr & GICH_VTR_NRLRGS) + 1;
@@ -836,7 +837,14 @@ static void gicv3_hyp_init(void)
         panic("GICv3: Invalid number of priority bits\n");
 
     WRITE_SYSREG32(GICH_VMCR_EOI | GICH_VMCR_VENG1, ICH_VMCR_EL2);
-    WRITE_SYSREG32(GICH_HCR_EN, ICH_HCR_EL2);
+
+    if ( cpus_have_cap(ARM64_WORKAROUND_CAVIUM_30115) )
+    {
+        hcr |= GICH_HCR_TALL1;
+        hcr |= GICH_HCR_TALL0;
+    }
+
+     WRITE_SYSREG32(hcr, ICH_HCR_EL2);
 }
 
 /* Set up the per-CPU parts of the GIC for a secondary CPU */
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index d3d7bda50d..c76a330b6b 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -117,6 +117,8 @@
 #define GICH_HCR_VGRP0DIE (1 << 5)
 #define GICH_HCR_VGRP1EIE (1 << 6)
 #define GICH_HCR_VGRP1DIE (1 << 7)
+#define GICH_HCR_TALL1    (1 << 12)
+#define GICH_HCR_TALL0    (1 << 11)
 
 #define GICH_MISR_EOI     (1 << 0)
 #define GICH_MISR_U       (1 << 1)
-- 
2.14.1


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