Re: [Xen-devel] [PATCH v2 12/17] arm64: vgic-v3: Add misc Group-0 handlers

[Manish Jaggi <mjaggi@xxxxxxxxxxxxxxxxxx>]

On 03/27/2018 04:28 PM, Marc Zyngier wrote:
> On 27/03/18 10:07, Manish Jaggi wrote:
> > This patch is ported to xen from linux commit:
> > eab0b2dc4f6f34147e3d10da49ab8032e15dbea0
> > (KVM: arm64: vgic-v3: Add misc Group-0 handlers)
> >
> > A number of Group-0 registers can be handled by the same accessors
> > as that of Group-1, so let's add the required system register encodings
> > and catch them in the dispatching function.
> >
> > Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx>
> > ---
> >   xen/arch/arm/arm64/vgic-v3-sr.c     | 7 +++++++
> >   xen/include/asm-arm/arm64/sysregs.h | 4 ++++
> >   2 files changed, 11 insertions(+)
> >
> > diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
> > index d854b1070d..201194c713 100644
> > --- a/xen/arch/arm/arm64/vgic-v3-sr.c
> > +++ b/xen/arch/arm/arm64/vgic-v3-sr.c
> > @@ -793,30 +793,37 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs 
> > *regs)
> >           vreg_emulate_igrpen1(regs, hsr);
> >           break;
> >   
> > +    case HSR_SYSREG_ICC_IAR0_EL1:
> >       case HSR_SYSREG_ICC_IAR1_EL1:
> >           vreg_emulate_iar(regs, hsr);
> >           break;
> >   
> > +    case HSR_SYSREG_ICC_EOIR0_EL1:
> >       case HSR_SYSREG_ICC_EOIR1_EL1:
> >           vreg_emulate_eoi(regs, hsr);
> >           break;
> >   
> > +    case HSR_SYSREG_ICC_AP0Rn_EL1(0):
> >       case HSR_SYSREG_ICC_AP1Rn_EL1(0):
> >           vreg_emulate_apxr0(regs, hsr);
> >           break;
> >   
> > +    case HSR_SYSREG_ICC_AP0Rn_EL1(1):
> >       case HSR_SYSREG_ICC_AP1Rn_EL1(1):
> >           vreg_emulate_apxr1(regs, hsr);
> >           break;
> >   
> > +    case HSR_SYSREG_ICC_AP0Rn_EL1(2):
> >       case HSR_SYSREG_ICC_AP1Rn_EL1(2):
> >           vreg_emulate_apxr2(regs, hsr);
> >           break;
> >   
> > +    case HSR_SYSREG_ICC_AP0Rn_EL1(3):
> >       case HSR_SYSREG_ICC_AP1Rn_EL1(3):
> >           vreg_emulate_apxr3(regs, hsr);
> >           break;
> >   
> > +    case HSR_SYSREG_ICC_HPPIR0_EL1:
> >       case HSR_SYSREG_ICC_HPPIR1_EL1:
> >           vreg_emulate_hppir1(regs, hsr);
> This doesn't shock you a tiny bit?
Ah, it should be vgic_emulate_hppir.
>         M.

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