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Re: [Xen-devel] [PATCH] x86/cpu: Support a new cpu vendor, which is Shanghai

>>> "Fiona Li(BJ-RD)" <FionaLi@xxxxxxxxxxx> 04/10/18 3:08 AM >>>
>> +static void init_shanghai(struct cpuinfo_x86 *c) {
>> +uint64_t msr_ace,msr_rng;
>> +/* Test for Shanghai Extended CPUID information */
>> +if (cpuid_eax(0xC0000000) >= 0xC0000001) {
>> +/*Get Shanghai Extended function number */
>> +u32 extented_feature_flags = cpuid_edx(0xC0000001);
>> +
>> +/* enable ACE,if support ACE unit */
>> +if(ACE_PRESENT(extented_feature_flags) && 
>> !ACE_ENABLED(extented_feature_flags)){
>> +rdmsrl(MSR_ZX_ACE, msr_ace);
>> +/* enable ACE  */
>> +wrmsrl(MSR_ZX_ACE, (msr_ace | ACE_FCR));
>>> +printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n");
>> +}
>> +/* enable RNG,if support RNG unit */
>> +if (RNG_PRESENT(extented_feature_flags) && 
>> !RNG_ENABLED(extented_feature_flags)) {
>> +rdmsrl(MSR_ZX_RNG, msr_rng);
>> +/* enable RNG  */
>> +wrmsrl(MSR_ZX_RNG, msr_rng | RNG_ENABLE);
>> +printk(KERN_INFO "CPU: Enabled h/w RNG\n");
>> +}
>> +}
>> +
>> +if (c->x86 == 0x6 && c->x86_model >= 0xf) {
>> +c->x86_cache_alignment = c->x86_clflush_size * 2;
>> +__set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
>> +}
>Is there a specification available anywhere for all of the above?
>[FionaLi]: Main usage of Zhaoxin platforms in recent years is for limited and 
>instead of distributed markets. So there is no such document for public access 
>present. But, Zhaoxin's x86 CPU is compatible with Intel x86 architecture. Its 
>sets are compatible with Intel. Furthermore, Zhaoxin's CPU virtualization tech 
>and I/O
>virtualization tech are compatible with Intel VMX and VT-d respectively. So 
>maybe we
>can refer to Intel manual at present.

Notw how I had said "for all of the above": The extensions are clearly not in 
the Intel
docs, and the cache alignment and TSC properties aren't general x86 attributes 

>What about guests? How would they know these extensions are available for 
>their use?
>[FionaLi]: My colleagues is committing code to Linux kernel and windows. Its 
>will be available to guests.

That wasn't the point of the question: Even with aware guest OSes you first of 
all need
to make sure guests can actually obtain the respective CPUID leaves. Afaict the
C000xxxx range will come out as all zeros for them without you doing something 
it. It is also questionable whether blanket enabling of the features for all 
guests is a
good step - I think this should be left to guest OSes (requiring you to 
properly emulate
their MSR accesses within Xen, unless the MSRs can be made directly accessible 
guests without security risks).


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