Re: [Xen-devel] [PATCH] x86/cpu: Support a new cpu vendor, which is Shanghai

["Fiona Li(BJ-RD)" <FionaLi@xxxxxxxxxxx>]

Jan
Thanks for your reply.  Answer the following.
Best wish!
FionaLi

-----Original Message-----
From: Jan Beulich [mailto:jbeulich@xxxxxxxx]
Sent: Tuesday, April 10, 2018 2:35 PM
To: lifang110@xxxxxxx; Fiona Li(BJ-RD) <FionaLi@xxxxxxxxxxx>
Cc: xen-devel@xxxxxxxxxxxxxxxxxxxx
Subject: Re: RE: [PATCH] x86/cpu: Support a new cpu vendor,which is Shanghai

>>> "Fiona Li(BJ-RD)" <FionaLi@xxxxxxxxxxx> 04/10/18 3:08 AM >>>
>> +static void init_shanghai(struct cpuinfo_x86 *c) { uint64_t
>> +msr_ace,msr_rng;
>> +/* Test for Shanghai Extended CPUID information */ if
>> +(cpuid_eax(0xC0000000) >= 0xC0000001) { /*Get Shanghai Extended
>> +function number */
>> +u32 extented_feature_flags = cpuid_edx(0xC0000001);
>> +
>> +/* enable ACE,if support ACE unit */
>> +if(ACE_PRESENT(extented_feature_flags) &&
>> +!ACE_ENABLED(extented_feature_flags)){
>> +rdmsrl(MSR_ZX_ACE, msr_ace);
>> +/* enable ACE  */
>> +wrmsrl(MSR_ZX_ACE, (msr_ace | ACE_FCR));
>>> +printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n");ai
>> +}
>> +/* enable RNG,if support RNG unit */ if
>> +(RNG_PRESENT(extented_feature_flags) &&
>> +!RNG_ENABLED(extented_feature_flags)) { rdmsrl(MSR_ZX_RNG, msr_rng);
>> +/* enable RNG  */
>> +wrmsrl(MSR_ZX_RNG, msr_rng | RNG_ENABLE); printk(KERN_INFO "CPU:
>> +Enabled h/w RNG\n"); } }
>> +
>> +if (c->x86 == 0x6 && c->x86_model >= 0xf) {
>> +c->x86_cache_alignment = c->x86_clflush_size * 2;
>> +__set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); }
>
>Is there a specification available anywhere for all of the above?
>[FionaLi]: Main usage of Zhaoxin platforms in recent years is for
>limited and embedded instead of distributed markets. So there is no
>such document for public access at present. But, Zhaoxin's x86 CPU is
>compatible with Intel x86 architecture. Its instruction sets are
>compatible with Intel. Furthermore, Zhaoxin's CPU virtualization tech
>and I/O virtualization tech are compatible with Intel VMX and VT-d 
>respectively. So maybe we can refer to Intel manual at present.

Notw how I had said "for all of the above": The extensions are clearly not in 
the Intel docs, and the cache alignment and TSC properties aren't general x86 
attributes either.
[FionaLi]:
For cache alignment, it is equal to the size of cache line on Zhaoxin platform. 
Since it has been initialized in early_cpu_detect(), we should remove this 
modification in next version patch.
For X86_FEATURE_CONSTANT_TSC, It  is an additional feature of TSC timer. For 
Shanghai CPU, it should be set according to X86_FEATURE_ITSC feature as Intel 
in next version patch.
Simple CPUID document in attached file is for your reference, the features 
supported by Shanghai CPU can be got from this doc.

>What about guests? How would they know these extensions are available for 
>their use?
>[FionaLi]: My colleagues is committing code to Linux kernel and
>windows. Its extensions will be available to guests.

That wasn't the point of the question: Even with aware guest OSes you first of 
all need to make sure guests can actually obtain the respective CPUID leaves. 
Afaict the C000xxxx range will come out as all zeros for them without you doing 
something about it. It is also questionable whether blanket enabling of the 
features for all guests is a good step - I think this should be left to guest 
OSes (requiring you to properly emulate their MSR accesses within Xen, unless 
the MSRs can be made directly accessible to guests without security risks).
[FionaLi] : I am sorry. I understood wrongly. The C000xxxx range are 
extensions, which provide some additional feature different from Intel.  As you 
suggested, we will enable those features in guest OSes and remove these code 
from patch. Can we support the CPUID leaves and emulate the MSR  with another 
submit?



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Attachment: zhaoxin_cpuid_leaf_description.xlsx
Description: zhaoxin_cpuid_leaf_description.xlsx

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