[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v3 10/17] arm64: vgic-v3: Add ICV_IGRPEN0_EL1 handler
This patch is ported to xen from linux commit: fbc48a0011deb3d51cb657ca9c0f9083f41c0665 Add a handler for reading/writing the guest's view of the ICC_IGRPEN0_EL1 register, which is located in the ICH_VMCR_EL2.VENG0 field. Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx> diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index f3b6e5367c..0fd3f929e4 100644 --- a/xen/arch/arm/arm64/vgic-v3-sr.c +++ b/xen/arch/arm/arm64/vgic-v3-sr.c @@ -641,6 +641,25 @@ spurious: set_user_reg(regs, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK); } +static void vgic_v3_read_igrpen0(struct cpu_user_regs *regs, uint32_t vmcr, + int rt) +{ + set_user_reg(regs, rt, !!(vmcr & ICH_VMCR_ENG0_MASK)); +} + +static void vgic_v3_write_igrpen0(struct cpu_user_regs *regs, uint32_t vmcr, + int rt) +{ + register_t val = get_user_reg(regs, rt); + + if ( val & 1 ) + vmcr |= ICH_VMCR_ENG0_MASK; + else + vmcr &= ~ICH_VMCR_ENG0_MASK; + + WRITE_SYSREG32(vmcr, ICH_VMCR_EL2); +} + /* vgic_v3_handle_cpuif_access * returns: true if the register is emulated * false if not a sysreg @@ -701,6 +720,13 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs) fn = vgic_v3_read_hppir; break; + case HSR_SYSREG_ICC_IGRPEN0_EL1: + if (is_read) + fn = vgic_v3_read_igrpen0; + else + fn = vgic_v3_write_igrpen0; + break; + default: ret = false; goto end; diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h index e03b6edf4d..3c4b5587a1 100644 --- a/xen/include/asm-arm/arm64/sysregs.h +++ b/xen/include/asm-arm/arm64/sysregs.h @@ -90,6 +90,7 @@ #define HSR_SYSREG_ICC_SGI0R_EL1 HSR_SYSREG(3,2,c12,c11,7) #define HSR_SYSREG_ICC_SRE_EL1 HSR_SYSREG(3,0,c12,c12,5) #define HSR_SYSREG_ICC_BPR1_EL1 HSR_SYSREG(3,0,c12,c12,3) +#define HSR_SYSREG_ICC_IGRPEN0_EL1 HSR_SYSREG(3,0,c12,c12,6) #define HSR_SYSREG_ICC_IGRPEN1_EL1 HSR_SYSREG(3,0,c12,c12,7) #define HSR_SYSREG_ICC_IAR1_EL1 HSR_SYSREG(3,0,c12,c12,0) #define HSR_SYSREG_ICC_EOIR1_EL1 HSR_SYSREG(3,0,c12,c12,1) -- 2.14.1 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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