[Xen-devel] [PATCH v3 11/17] arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler

[Manish Jaggi <mjaggi@xxxxxxxxxxxxxxxxxx>]

This patch is a xen port of linux commit
f9e7449c780f688bf61a13dfa8c344afeb4ad6e0.

Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1
registers. We just map them to the corresponding ICH_AP(1)Rn_EL2
registers.

Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx>

diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 0fd3f929e4..a09d7544f3 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -660,6 +660,78 @@ static void vgic_v3_write_igrpen0(struct cpu_user_regs 
*regs, uint32_t vmcr,
     WRITE_SYSREG32(vmcr, ICH_VMCR_EL2);
 }
 
+static void vgic_v3_read_apxrn(struct cpu_user_regs *regs, int rt, int n)
+{
+    uint32_t val;
+    const union hsr hsr = { .bits = regs->hsr };
+
+    if ( !vgic_v3_get_group(hsr) )
+        val = vgic_v3_read_ap0rn(n);
+    else
+        val = vgic_v3_read_ap1rn(n);
+
+    set_user_reg(regs, rt, val);
+}
+
+static void vgic_v3_write_apxrn(struct cpu_user_regs *regs, int rt, int n)
+{
+    u32 val = get_user_reg(regs, rt);
+    const union hsr hsr = { .bits = regs->hsr };
+
+    if ( !vgic_v3_get_group(hsr) )
+        vgic_v3_write_ap0rn(val, n);
+    else
+        vgic_v3_write_ap1rn(val, n);
+}
+
+static void vgic_v3_read_apxr0(struct cpu_user_regs *regs, uint32_t vmcr,
+                               int rt)
+{
+    vgic_v3_read_apxrn(regs, rt, 0);
+}
+
+static void vgic_v3_read_apxr1(struct cpu_user_regs *regs, uint32_t vmcr,
+                               int rt)
+{
+    vgic_v3_read_apxrn(regs, rt, 1);
+}
+
+static void vgic_v3_read_apxr2(struct cpu_user_regs *regs, uint32_t vmcr,
+                               int rt)
+{
+    vgic_v3_read_apxrn(regs, rt, 2);
+}
+
+static void vgic_v3_read_apxr3(struct cpu_user_regs *regs, uint32_t vmcr,
+                               int rt)
+{
+    vgic_v3_read_apxrn(regs, rt, 3);
+}
+
+static void vgic_v3_write_apxr0(struct cpu_user_regs *regs, uint32_t vmcr,
+                                int rt)
+{
+    vgic_v3_write_apxrn(regs, rt, 0);
+}
+
+static void vgic_v3_write_apxr1(struct cpu_user_regs *regs, uint32_t vmcr,
+                                int rt)
+{
+    vgic_v3_write_apxrn(regs, rt, 1);
+}
+
+static void vgic_v3_write_apxr2(struct cpu_user_regs *regs, uint32_t vmcr,
+                                int rt)
+{
+    vgic_v3_write_apxrn(regs, rt, 2);
+}
+
+static void vgic_v3_write_apxr3(struct cpu_user_regs *regs, uint32_t vmcr,
+                                int rt)
+{
+    vgic_v3_write_apxrn(regs, rt, 3);
+}
+
 /* vgic_v3_handle_cpuif_access
  * returns: true if the register is emulated
  *          false if not a sysreg
@@ -727,6 +799,34 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs 
*regs)
             fn = vgic_v3_write_igrpen0;
         break;
 
+    case HSR_SYSREG_ICC_AP1Rn_EL1(0):
+        if (is_read)
+            fn = vgic_v3_read_apxr0;
+        else
+            fn = vgic_v3_write_apxr0;
+        break;
+
+    case HSR_SYSREG_ICC_AP1Rn_EL1(1):
+        if (is_read)
+            fn = vgic_v3_read_apxr1;
+        else
+            fn = vgic_v3_write_apxr1;
+        break;
+
+    case HSR_SYSREG_ICC_AP1Rn_EL1(2):
+        if (is_read)
+            fn = vgic_v3_read_apxr2;
+        else
+            fn = vgic_v3_write_apxr2;
+        break;
+
+    case HSR_SYSREG_ICC_AP1Rn_EL1(3):
+        if (is_read)
+            fn = vgic_v3_read_apxr3;
+        else
+            fn = vgic_v3_write_apxr3;
+        break;
+
     default:
         ret = false;
         goto end;
diff --git a/xen/include/asm-arm/arm64/sysregs.h 
b/xen/include/asm-arm/arm64/sysregs.h
index 3c4b5587a1..0e583f820d 100644
--- a/xen/include/asm-arm/arm64/sysregs.h
+++ b/xen/include/asm-arm/arm64/sysregs.h
@@ -97,6 +97,7 @@
 #define HSR_SYSREG_ICC_HPPIR1_EL1 HSR_SYSREG(3,0,c12,c12,2)
 #define HSR_SYSREG_ICC_BPR0_EL1          HSR_SYSREG(3,0,c12,c8,3)
 #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
+#define HSR_SYSREG_ICC_AP1Rn_EL1(n) HSR_SYSREG(3,0,c12,c9, n)
 
 #define HSR_SYSREG_PMCR_EL0       HSR_SYSREG(3,3,c9,c12,0)
 #define HSR_SYSREG_PMCNTENSET_EL0 HSR_SYSREG(3,3,c9,c12,1)
-- 
2.14.1


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