[Xen-devel] [PATCH v3 12/17] arm64: vgic-v3: Add misc Group-0 handlers

[Manish Jaggi <mjaggi@xxxxxxxxxxxxxxxxxx>]

This patch is ported to xen from linux commit:
eab0b2dc4f6f34147e3d10da49ab8032e15dbea0

A number of Group-0 registers can be handled by the same accessors
as that of Group-1, so let's add the required system register encodings
and catch them in the dispatching function.

Signed-off-by: Manish Jaggi <manish.jaggi@xxxxxxxxxx>

diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index a09d7544f3..27f5139dcb 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -780,14 +780,17 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs 
*regs)
             fn = vgic_v3_write_igrpen1;
         break;
 
+    case HSR_SYSREG_ICC_IAR0_EL1:
     case HSR_SYSREG_ICC_IAR1_EL1:
         fn = vgic_v3_read_iar;
         break;
 
+    case HSR_SYSREG_ICC_EOIR0_EL1:
     case HSR_SYSREG_ICC_EOIR1_EL1:
         fn = vgic_v3_write_eoir;
         break;
 
+    case HSR_SYSREG_ICC_HPPIR0_EL1:
     case HSR_SYSREG_ICC_HPPIR1_EL1:
         fn = vgic_v3_read_hppir;
         break;
@@ -799,6 +802,7 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs)
             fn = vgic_v3_write_igrpen0;
         break;
 
+    case HSR_SYSREG_ICC_AP0Rn_EL1(0):
     case HSR_SYSREG_ICC_AP1Rn_EL1(0):
         if (is_read)
             fn = vgic_v3_read_apxr0;
@@ -806,6 +810,7 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs)
             fn = vgic_v3_write_apxr0;
         break;
 
+    case HSR_SYSREG_ICC_AP0Rn_EL1(1):
     case HSR_SYSREG_ICC_AP1Rn_EL1(1):
         if (is_read)
             fn = vgic_v3_read_apxr1;
@@ -813,6 +818,7 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs)
             fn = vgic_v3_write_apxr1;
         break;
 
+    case HSR_SYSREG_ICC_AP0Rn_EL1(2):
     case HSR_SYSREG_ICC_AP1Rn_EL1(2):
         if (is_read)
             fn = vgic_v3_read_apxr2;
@@ -820,6 +826,7 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs)
             fn = vgic_v3_write_apxr2;
         break;
 
+    case HSR_SYSREG_ICC_AP0Rn_EL1(3):
     case HSR_SYSREG_ICC_AP1Rn_EL1(3):
         if (is_read)
             fn = vgic_v3_read_apxr3;
diff --git a/xen/include/asm-arm/arm64/sysregs.h 
b/xen/include/asm-arm/arm64/sysregs.h
index 0e583f820d..f83326943a 100644
--- a/xen/include/asm-arm/arm64/sysregs.h
+++ b/xen/include/asm-arm/arm64/sysregs.h
@@ -95,9 +95,13 @@
 #define HSR_SYSREG_ICC_IAR1_EL1   HSR_SYSREG(3,0,c12,c12,0)
 #define HSR_SYSREG_ICC_EOIR1_EL1  HSR_SYSREG(3,0,c12,c12,1)
 #define HSR_SYSREG_ICC_HPPIR1_EL1 HSR_SYSREG(3,0,c12,c12,2)
+#define HSR_SYSREG_ICC_IAR0_EL1   HSR_SYSREG(3,0,c12,c8,0)
+#define HSR_SYSREG_ICC_EOIR0_EL1  HSR_SYSREG(3,0,c12,c8,1)
+#define HSR_SYSREG_ICC_HPPIR0_EL1 HSR_SYSREG(3,0,c12,c8,2)
 #define HSR_SYSREG_ICC_BPR0_EL1          HSR_SYSREG(3,0,c12,c8,3)
 #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
 #define HSR_SYSREG_ICC_AP1Rn_EL1(n) HSR_SYSREG(3,0,c12,c9, n)
+#define HSR_SYSREG_ICC_AP0Rn_EL1(n) HSR_SYSREG(3,0,c12,c8,4|n)
 
 #define HSR_SYSREG_PMCR_EL0       HSR_SYSREG(3,3,c9,c12,0)
 #define HSR_SYSREG_PMCNTENSET_EL0 HSR_SYSREG(3,3,c9,c12,1)
-- 
2.14.1


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