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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v2 03/10] x86: Add Intel Processor Trace support for cpuid
Intel Processor Trace will be disabled in guest
when ipt_mode is off (IPT_MODE_OFF).
Signed-off-by: Luwei Kang <luwei.kang@xxxxxxxxx>
---
tools/libxc/xc_cpuid_x86.c | 12 ++++++++++--
xen/arch/x86/cpuid.c | 22 ++++++++++++++++++++++
xen/arch/x86/domctl.c | 5 +++++
xen/include/asm-x86/cpufeature.h | 1 +
xen/include/asm-x86/cpuid.h | 12 +++++++++++-
xen/include/asm-x86/ipt.h | 2 ++
xen/include/public/arch-x86/cpufeatureset.h | 1 +
7 files changed, 52 insertions(+), 3 deletions(-)
diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 9fa2f7c..f8f962a 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -38,7 +38,7 @@ enum {
#define clear_feature(idx, dst) ((dst) &= ~bitmaskof(idx))
#define set_feature(idx, dst) ((dst) |= bitmaskof(idx))
-#define DEF_MAX_BASE 0x0000000du
+#define DEF_MAX_BASE 0x00000014u
#define DEF_MAX_INTELEXT 0x80000008u
#define DEF_MAX_AMDEXT 0x8000001cu
@@ -473,6 +473,7 @@ static void xc_cpuid_hvm_policy(xc_interface *xch,
case 0x00000002: /* Intel cache info (dumped by AMD policy) */
case 0x00000004: /* Intel cache info (dumped by AMD policy) */
case 0x0000000a: /* Architectural Performance Monitor Features */
+ case 0x00000014: /* Intel Processor Trace Features */
case 0x80000002: /* Processor name string */
case 0x80000003: /* ... continued */
case 0x80000004: /* ... continued */
@@ -759,12 +760,19 @@ int xc_cpuid_apply_policy(xc_interface *xch, uint32_t
domid,
continue;
}
+ if ( input[0] == 0x14 )
+ {
+ input[1]++;
+ if ( input[1] == 1 )
+ continue;
+ }
+
input[0]++;
if ( !(input[0] & 0x80000000u) && (input[0] > base_max ) )
input[0] = 0x80000000u;
input[1] = XEN_CPUID_INPUT_UNUSED;
- if ( (input[0] == 4) || (input[0] == 7) )
+ if ( (input[0] == 4) || (input[0] == 7) || (input[0] == 0x14) )
input[1] = 0;
else if ( input[0] == 0xd )
input[1] = 1; /* Xen automatically calculates almost everything. */
diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index 4b8d330..8f30f9e 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -6,6 +6,7 @@
#include <asm/hvm/nestedhvm.h>
#include <asm/hvm/svm/svm.h>
#include <asm/hvm/vmx/vmcs.h>
+#include <asm/ipt.h>
#include <asm/paging.h>
#include <asm/processor.h>
#include <asm/xstate.h>
@@ -583,7 +584,19 @@ void recalculate_cpuid_policy(struct domain *d)
__clear_bit(X86_FEATURE_VMX, max_fs);
__clear_bit(X86_FEATURE_SVM, max_fs);
}
+
+ /*
+ * Hide Intel Processor trace feature when hardware not support
+ * PT-VMX or ipt option is off.
+ */
+ if ( ipt_mode == IPT_MODE_OFF )
+ {
+ __clear_bit(X86_FEATURE_IPT, max_fs);
+ zero_leaves(p->ipt.raw, 0, ARRAY_SIZE(p->ipt.raw) - 1);
+ }
}
+ else
+ zero_leaves(p->ipt.raw, 0, ARRAY_SIZE(p->ipt.raw) - 1);
/*
* Allow the toolstack to set HTT, X2APIC and CMP_LEGACY. These bits
@@ -738,6 +751,15 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
*res = p->feat.raw[subleaf];
break;
+ case IPT_CPUID:
+ ASSERT(p->ipt.max_subleaf < ARRAY_SIZE(p->ipt.raw));
+ if ( subleaf > min_t(uint32_t, p->ipt.max_subleaf,
+ ARRAY_SIZE(p->ipt.raw) - 1) )
+ return;
+
+ *res = p->ipt.raw[subleaf];
+ break;
+
case XSTATE_CPUID:
if ( !p->basic.xsave || subleaf >= ARRAY_SIZE(p->xstate.raw) )
return;
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 8fbbf3a..51743be 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -35,6 +35,7 @@
#include <asm/debugger.h>
#include <asm/psr.h>
#include <asm/cpuid.h>
+#include <asm/ipt.h>
static int gdbsx_guest_mem_io(domid_t domid, struct xen_domctl_gdbsx_memio
*iop)
{
@@ -101,6 +102,10 @@ static int update_domain_cpuid_info(struct domain *d,
p->feat.raw[ctl->input[1]] = leaf;
break;
+ case IPT_CPUID:
+ p->ipt.raw[ctl->input[1]] = leaf;
+ break;
+
case XSTATE_CPUID:
p->xstate.raw[ctl->input[1]] = leaf;
break;
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 2cf8f7e..97610d8 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -102,6 +102,7 @@
#define cpu_has_mpx boot_cpu_has(X86_FEATURE_MPX)
#define cpu_has_rdseed boot_cpu_has(X86_FEATURE_RDSEED)
#define cpu_has_smap boot_cpu_has(X86_FEATURE_SMAP)
+#define cpu_has_ipt boot_cpu_has(X86_FEATURE_IPT)
#define cpu_has_sha boot_cpu_has(X86_FEATURE_SHA)
/* CPUID level 0x80000007.edx */
diff --git a/xen/include/asm-x86/cpuid.h b/xen/include/asm-x86/cpuid.h
index 4cce268..c19ef28 100644
--- a/xen/include/asm-x86/cpuid.h
+++ b/xen/include/asm-x86/cpuid.h
@@ -58,10 +58,11 @@ DECLARE_PER_CPU(struct cpuidmasks, cpuidmasks);
/* Default masking MSR values, calculated at boot. */
extern struct cpuidmasks cpuidmask_defaults;
-#define CPUID_GUEST_NR_BASIC (0xdu + 1)
+#define CPUID_GUEST_NR_BASIC (0x14u + 1)
#define CPUID_GUEST_NR_FEAT (0u + 1)
#define CPUID_GUEST_NR_CACHE (5u + 1)
#define CPUID_GUEST_NR_XSTATE (62u + 1)
+#define CPUID_GUEST_NR_IPT (1u + 1)
#define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1)
#define CPUID_GUEST_NR_EXTD_AMD (0x1cu + 1)
#define CPUID_GUEST_NR_EXTD MAX(CPUID_GUEST_NR_EXTD_INTEL, \
@@ -166,6 +167,15 @@ struct cpuid_policy
} comp[CPUID_GUEST_NR_XSTATE];
} xstate;
+ /* Structured feature leaf: 0x00000014[xx] */
+ union {
+ struct cpuid_leaf raw[CPUID_GUEST_NR_IPT];
+ struct {
+ /* Subleaf 0. */
+ uint32_t max_subleaf;
+ };
+ } ipt;
+
/* Extended leaves: 0x800000xx */
union {
struct cpuid_leaf raw[CPUID_GUEST_NR_EXTD];
diff --git a/xen/include/asm-x86/ipt.h b/xen/include/asm-x86/ipt.h
index c46b9fc..65b064c 100644
--- a/xen/include/asm-x86/ipt.h
+++ b/xen/include/asm-x86/ipt.h
@@ -24,6 +24,8 @@
#define IPT_MODE_OFF 0
#define IPT_MODE_GUEST (1<<0)
+#define IPT_CPUID 0x00000014
+
extern unsigned int ipt_mode;
#endif /* __ASM_X86_HVM_IPT_H_ */
diff --git a/xen/include/public/arch-x86/cpufeatureset.h
b/xen/include/public/arch-x86/cpufeatureset.h
index c721c12..a1643a5 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -215,6 +215,7 @@ XEN_CPUFEATURE(SMAP, 5*32+20) /*S Supervisor Mode
Access Prevention */
XEN_CPUFEATURE(AVX512IFMA, 5*32+21) /*A AVX-512 Integer Fused Multiply Add
*/
XEN_CPUFEATURE(CLFLUSHOPT, 5*32+23) /*A CLFLUSHOPT instruction */
XEN_CPUFEATURE(CLWB, 5*32+24) /*A CLWB instruction */
+XEN_CPUFEATURE(IPT, 5*32+25) /*H Intel Processor Trace */
XEN_CPUFEATURE(AVX512PF, 5*32+26) /*A AVX-512 Prefetch Instructions */
XEN_CPUFEATURE(AVX512ER, 5*32+27) /*A AVX-512 Exponent & Reciprocal
Instrs */
XEN_CPUFEATURE(AVX512CD, 5*32+28) /*A AVX-512 Conflict Detection Instrs
*/
--
1.8.3.1
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