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Re: [Xen-devel] [PATCH] x86emul: permit SAE for V{,U}COMIS{S,D}

  • To: <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Date: Wed, 19 Dec 2018 12:02:45 +0000
  • Autocrypt: addr=andrew.cooper3@xxxxxxxxxx; prefer-encrypt=mutual; keydata= mQINBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABtClBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPokCOgQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86LkCDQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAYkC HwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA==
  • Delivery-date: Wed, 19 Dec 2018 12:03:02 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
  • Openpgp: preference=signencrypt

On 18/12/2018 15:22, Jan Beulich wrote:
>>>> On 18.12.18 at 15:28, <andrew.cooper3@xxxxxxxxxx> wrote:
>> On 10/12/2018 13:56, Jan Beulich wrote:
>>>>>> On 10.12.18 at 14:20, <andrew.cooper3@xxxxxxxxxx> wrote:
>>>> On 10/12/2018 11:32, Jan Beulich wrote:
>>>>> The avx512_vlen_check() invocation needs to be conditional.
>>>>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
>>>> I'm not sure if I've asked before, but do LIG instructions really #UD
>>>> for L=3 ?  I don't see any documentation to this effect.
>>> At least on my Core i9 they do; I have a pending query with Intel
>>> as to the intentions in general and the lack of clear documentation,
>>> as well as to the behavior on the Knights line of processors (where
>>> there is no AVX512VL, and hence where special casing VL=128 and
>>> VL=256 but not VL=<whatever-3-will- mean> are at least
>>> questionable).
>> VL=3 will surely be 1024 bits wide, but I'd be interested to which
>> register mnemonic they choose to follow xmm/ymm/zmm.
>> I'll try to find some time to poke a Knights machine and see what happens.
>>>>> --- a/xen/arch/x86/x86_emulate/x86_emulate.c
>>>>> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c
>>>>> @@ -6179,7 +6179,8 @@ x86_emulate(
>>>>>                                 evex.w != evex.pfx),
>>>>>                                EXC_UD);
>>>>>          host_and_vcpu_must_have(avx512f);
>>>>> -        avx512_vlen_check(true);
>>>>> +        if ( !evex.br )
>>>> On the subject of ineligibility of the code, what about #define sae br ?
>>>> That way, this would read "if ( !evex.sae ) check_vlen()"
>>> The three meanings of the bit can't reasonably all be conveyed
>>> by a acceptably short name. Of course we can introduce aliases
>>> like the above, but please recall that
>>> - "br" stands for _b_roadcast or _r_ounding, not _br_oadcast,
>> TBH, I'd even forgotten this.  I don't see it written anywhere.  Despite
>> what you claim, people will interpret it as _br_oadcast given a lack of
>> any information to the contrary.
>>> - we'd need another alias for the embedded-rounding case then.
>>> If you're convinced this is a good idea, I can do respective
>>> renaming both to what may already be committed as well as to
>>> the rest of the still pending series.
>>> But personally I'd rather not go that route, to make it easier to
>>> connect with one another all the uses/checks of that bit. This is
>>> in particular because for insns which allow neither broadcast nor
>>> rounding/SAE, I certainly don't want to check the same bit twice
>>> (via its different names).
>> The context-dependent meanings are:
>> * Broadcast
>> * Static Rounding
>> * Suppress All Exceptions
>> How about naming the field bsr for "broadcast/suppress/rounding" (which
>> breaks the _br_oadcast vs _b_roadcast/_r_ounding confusion), and
>> introducing a define for bcast, sae and rounding ?
> Well, yes, I'd been considering "brs" (I dislike "bsr" for its collision
> with the same name insn mnemonic).
>> /* EVEX.b (SDM nomenclature) has encoding-dependent meaning. */
>> #define bcast bsr
>> #define sae bsr
>> #define rounding bsr
>> That way, code with a single meaning can use the context-correct name,
>> and any cases (are there any?) which don't use one of these modes can
>> use the underlying field.
> Well, it's the common case that the field has two meanings: SAE
> or ER with all register operands and BROADCAST with a memory
> one. Exceptions are when either broadcast or SAE/ER are not
> permitted for a particular major opcode.

Lovely... The SDM uses {er}, naming it "embedded rounding", for the
field referred to as Static Rounding in the EVEX chapter.  I think I'll
ask Intel to fix this.

How do we distinguish between SAE and ER then?  It looks like ER implies
SAE, and they are both only usable by scalar or full-width float operations.

>> I don't think it will cause confusion for correlating the uses of the
>> bit, because we will never be using more than a single name in one context.
>> To unblock the original patch (which shouldn't be conflated with this
>> suggested improvement), Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> Thanks. Question then is - are you convinced enough of your
> proposal for me to re-work things before posting v7 of the
> main series? And if so are you fine with "brs" instead of "bsr"
> (and perhaps "er" instead of "rounding", to be closer to SDM
> terminology)?

brs is fine as an alternative bsr.  It retains the important property of
not being able to be confused as "broadcast".

I suppose that at the point that we have sae, er is also fine, and as
you point out, it is closer to SDM terminology.


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