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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v4 1/4] x86: stop handling MSR_IA32_BNDCFGS save/restore in implementation code
Saving and restoring the value of this MSR is currently handled by
implementation-specific code despite it being architectural. This patch
moves handling of accesses to this MSR from hvm.c into the msr.c, thus
allowing the common MSR save/restore code to handle it.
NOTE: Because vmx_get/set_guest_bndcfgs() call vmx_vmcs_enter(), the
struct vcpu pointer passed in, and hence the vcpu pointer passed to
guest_rdmsr() cannot be const.
Signed-off-by: Paul Durrant <paul.durrant@xxxxxxxxxx>
---
Cc: Kevin Tian <kevin.tian@xxxxxxxxx>
Cc: Jan Beulich <jbeulich@xxxxxxxx>
Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Cc: Wei Liu <wei.liu2@xxxxxxxxxx>
Cc: "Roger Pau Monné" <roger.pau@xxxxxxxxxx>
Cc: Jun Nakajima <jun.nakajima@xxxxxxxxx>
v4:
- Cosmetic re-arrangements and an additional ASSERT requested by Jan
v3:
- Address further comments from Jan
- Dropped Kevin's R-b because of change to vmx.c
v2:
- Addressed comments from Jan by largely removing hunks
- Keeping Kevin's R-b since remaining hunks in vmx.c are as before
---
xen/arch/x86/hvm/hvm.c | 14 ++------------
xen/arch/x86/hvm/vmx/vmx.c | 24 ++++--------------------
xen/arch/x86/msr.c | 20 ++++++++++++++++++++
xen/include/asm-x86/hvm/hvm.h | 4 ++--
4 files changed, 28 insertions(+), 34 deletions(-)
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 8adbb61b57..e566d83f8b 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -1303,6 +1303,7 @@ static int hvm_load_cpu_xsave_states(struct domain *d,
hvm_domain_context_t *h)
static const uint32_t msrs_to_send[] = {
MSR_SPEC_CTRL,
MSR_INTEL_MISC_FEATURES_ENABLES,
+ MSR_IA32_BNDCFGS,
MSR_AMD64_DR0_ADDRESS_MASK,
MSR_AMD64_DR1_ADDRESS_MASK,
MSR_AMD64_DR2_ADDRESS_MASK,
@@ -1440,6 +1441,7 @@ static int hvm_load_cpu_msrs(struct domain *d,
hvm_domain_context_t *h)
case MSR_SPEC_CTRL:
case MSR_INTEL_MISC_FEATURES_ENABLES:
+ case MSR_IA32_BNDCFGS:
case MSR_AMD64_DR0_ADDRESS_MASK:
case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK:
rc = guest_wrmsr(v, ctxt->msr[i].index, ctxt->msr[i].val);
@@ -3467,12 +3469,6 @@ int hvm_msr_read_intercept(unsigned int msr, uint64_t
*msr_content)
*msr_content = v->arch.hvm.msr_xss;
break;
- case MSR_IA32_BNDCFGS:
- if ( !d->arch.cpuid->feat.mpx ||
- !hvm_get_guest_bndcfgs(v, msr_content) )
- goto gp_fault;
- break;
-
case MSR_K8_ENABLE_C1E:
case MSR_AMD64_NB_CFG:
/*
@@ -3619,12 +3615,6 @@ int hvm_msr_write_intercept(unsigned int msr, uint64_t
msr_content,
v->arch.hvm.msr_xss = msr_content;
break;
- case MSR_IA32_BNDCFGS:
- if ( !d->arch.cpuid->feat.mpx ||
- !hvm_set_guest_bndcfgs(v, msr_content) )
- goto gp_fault;
- break;
-
case MSR_AMD64_NB_CFG:
/* ignore the write */
break;
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 725dd88c13..f8481d032a 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -805,17 +805,6 @@ static unsigned int __init vmx_init_msr(void)
static void vmx_save_msr(struct vcpu *v, struct hvm_msr *ctxt)
{
- vmx_vmcs_enter(v);
-
- if ( cpu_has_mpx && cpu_has_vmx_mpx )
- {
- __vmread(GUEST_BNDCFGS, &ctxt->msr[ctxt->count].val);
- if ( ctxt->msr[ctxt->count].val )
- ctxt->msr[ctxt->count++].index = MSR_IA32_BNDCFGS;
- }
-
- vmx_vmcs_exit(v);
-
if ( cpu_has_xsaves && cpu_has_vmx_xsaves )
{
ctxt->msr[ctxt->count].val = v->arch.hvm.msr_xss;
@@ -835,14 +824,6 @@ static int vmx_load_msr(struct vcpu *v, struct hvm_msr
*ctxt)
{
switch ( ctxt->msr[i].index )
{
- case MSR_IA32_BNDCFGS:
- if ( cpu_has_mpx && cpu_has_vmx_mpx &&
- is_canonical_address(ctxt->msr[i].val) &&
- !(ctxt->msr[i].val & IA32_BNDCFGS_RESERVED) )
- __vmwrite(GUEST_BNDCFGS, ctxt->msr[i].val);
- else if ( ctxt->msr[i].val )
- err = -ENXIO;
- break;
case MSR_IA32_XSS:
if ( cpu_has_xsaves && cpu_has_vmx_xsaves )
v->arch.hvm.msr_xss = ctxt->msr[i].val;
@@ -1215,8 +1196,11 @@ static bool vmx_set_guest_bndcfgs(struct vcpu *v, u64
val)
return true;
}
-static bool vmx_get_guest_bndcfgs(struct vcpu *v, u64 *val)
+static bool vmx_get_guest_bndcfgs(const struct vcpu *cv, u64 *val)
{
+ /* Get a non-const pointer for vmx_vmcs_enter() */
+ struct vcpu *v = cv->domain->vcpu[cv->vcpu_id];
+
ASSERT(cpu_has_mpx && cpu_has_vmx_mpx);
vmx_vmcs_enter(v);
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index 4df4a59f4d..0e901d2397 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -160,6 +160,16 @@ int guest_rdmsr(const struct vcpu *v, uint32_t msr,
uint64_t *val)
ret = guest_rdmsr_x2apic(v, msr, val);
break;
+ case MSR_IA32_BNDCFGS:
+ if ( !cp->feat.mpx )
+ goto gp_fault;
+
+ ASSERT(is_hvm_domain(d));
+ if (!hvm_get_guest_bndcfgs(v, val) )
+ goto gp_fault;
+
+ break;
+
case 0x40000000 ... 0x400001ff:
if ( is_viridian_domain(d) )
{
@@ -323,6 +333,16 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
ret = guest_wrmsr_x2apic(v, msr, val);
break;
+ case MSR_IA32_BNDCFGS:
+ if ( !cp->feat.mpx )
+ goto gp_fault;
+
+ ASSERT(is_hvm_domain(d));
+ if ( !hvm_set_guest_bndcfgs(v, val) )
+ goto gp_fault;
+
+ break;
+
case 0x40000000 ... 0x400001ff:
if ( is_viridian_domain(d) )
{
diff --git a/xen/include/asm-x86/hvm/hvm.h b/xen/include/asm-x86/hvm/hvm.h
index 53ffebb2c5..d41ed63232 100644
--- a/xen/include/asm-x86/hvm/hvm.h
+++ b/xen/include/asm-x86/hvm/hvm.h
@@ -149,7 +149,7 @@ struct hvm_function_table {
int (*get_guest_pat)(struct vcpu *v, u64 *);
int (*set_guest_pat)(struct vcpu *v, u64);
- bool (*get_guest_bndcfgs)(struct vcpu *v, u64 *);
+ bool (*get_guest_bndcfgs)(const struct vcpu *v, u64 *);
bool (*set_guest_bndcfgs)(struct vcpu *v, u64);
void (*set_tsc_offset)(struct vcpu *v, u64 offset, u64 at_tsc);
@@ -448,7 +448,7 @@ static inline unsigned long hvm_get_shadow_gs_base(struct
vcpu *v)
return hvm_funcs.get_shadow_gs_base(v);
}
-static inline bool hvm_get_guest_bndcfgs(struct vcpu *v, u64 *val)
+static inline bool hvm_get_guest_bndcfgs(const struct vcpu *v, u64 *val)
{
return hvm_funcs.get_guest_bndcfgs &&
hvm_funcs.get_guest_bndcfgs(v, val);
--
2.20.1
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