Re: [Xen-devel] [PATCH v6 11/12] x86/microcode: Synchronize late microcode loading

[Thomas Gleixner <tglx@xxxxxxxxxxxxx>]

Ashok,

On Thu, 14 Mar 2019, Raj, Ashok wrote:
> On Thu, Mar 14, 2019 at 12:39:46PM +0000, Andrew Cooper wrote:
> > On late load failure, we should dump enough information to work out
> > exactly what went on, to determine how best to proceed, but the server
> > is effectively lost to us.  On late load success, the proposed new
> > "version" replaces the current "version".
> > 
> > And again - I reiterate the point that I think it is fine to have a
> > simplifying assumption that we don't have mixed stepping systems to
> > start with, presuming this is generally in line with Intel's support
> > statement.  If in practice we find mixed stepping systems which are
> > supported by an OEM/Intel, we can see about extending the logic.
> 
> Checking with Asit he says it is in fact permitted to have 1 step behind
> even on a multi-socket system. One could be N and other N-1 should be 
> supported.

That turns into a total disaster if N has an issue fixed ant N-1 requires
microcode + software workaround.

So if N is on the boot socket, then we fail to enable the workaround
because CPU0 has the 'Issue fixed' bit set.

If N-1 is on the boot socket, then we go to do the workaround nevertheless
on N and that might dependend on the issue just be some pointless exercise
or even try to access some MSR which is not available.

*Shudder*

        tglx

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