Re: [Xen-devel] [PATCH v2 02/14] x86/cpu/mtrr: Add Hygon Dhyana support to get TOP_MEM2

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 18.03.19 at 16:51, <puwen@xxxxxxxx> wrote:
> On 2019/3/18 16:57, Jan Beulich wrote:
>>>>> On 16.03.19 at 11:06, <puwen@xxxxxxxx> wrote:
>>> On 2019/3/15 20:40, Jan Beulich wrote:
>>>>>>> On 21.02.19 at 10:48, <puwen@xxxxxxxx> wrote:
>>>>> The Hygon Dhyana CPU supports the MSR way to get TOP_MEM2. So add Hygon
>>>>> Dhyana support to print the value of TOP_MEM2.
>>>>>
>>>>> Signed-off-by: Pu Wen <puwen@xxxxxxxx>
>>>>
>>>> Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
>>>>
>>>> I'm afraid I won't be able to offer Reviewed-by tags for any of
>>>> this series without you pointing us at the documentation for the
>>>> processor (a link should really be in the cover letter).
>>>
>>> Do you mean the specification for Hygon processor? We don't have any
>>> public spec now, but you can reference to the AMD Zen one[1].
>> 
>> Well, no, not really. There are undoubtedly differences (see your
>> reply to my pci_cfg_ok() question as an example). I can ack
>> changes on the basis that you know how your processors behave.
>> I can give R-b only if I have Hygon-specific doc to check against.
> 
> In fact there is no definition of MSR C001_001F(MSR_AMD64_NB_CFG) in the
> AMD family 17h models 00h-0Fh PPR, I don't know why there is 0x17 support
> in pci_cfg_ok().

Hmm, interesting observation. The extended access mechanism appears
to still exist, but is controlled by a different PCI config space bit now,
and there doesn't seem to be any mirroring MSR anymore. Brian, could
you confirm this? If there's indeed no NB_CFG MSR anymore, we may
need to adjust some of our code elsewhere as well; the control logic of
extended accesses looks to need adjustment in any event.

The use of 0x17 looks to date back to a 2010 commit (3157bb4e13),
where decimal 17 was converted to 0x17, without there being any
description to clarify whether this wasn't actually a mistake.

Jan



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