Re: [Xen-devel] [PATCH 3/3] mwait-idle: add enablement for AMD Naples and Rome

["Woods, Brian" <Brian.Woods@xxxxxxx>]

On 3/15/19 3:54 AM, Jan Beulich wrote:
>>>> On 14.03.19 at 20:29, <Brian.Woods@xxxxxxx> wrote:
>> On 3/13/19 4:51 AM, Jan Beulich wrote:
>>>>>> On 25.02.19 at 21:24, <Brian.Woods@xxxxxxx> wrote:
>>>> Add the needed data structures for enabling Naples (F17h M01h).  Since
>>>> Rome (F17h M31h) has the same c-state latencies and entry methods, the
>>>> c-state information can be used for Rome as well.  For both Naples and
>>>> Rome, mwait is used for c1 (cc1) and halt is functionally the same as
>>>> c2 (cc6).  If c2 (cc6) is disabled in BIOS, then halt functions similar
>>>> to c1 (cc1).
>>>
>>> But your code does not detect this situation, and does hence not update
>>> the table used accordingly. Why is this? Is entering C1 cheaper one way
>>> or the other in this situation (in which case the cheaper approach should
>>> always be used)?
>>
>> Well, if Xen had an AML interrupter, we could use the ACPI tables like
>> we do in Linux, but Xen doesn't (which is why we're hard coding it).
> 
> But the necessary data gets uploaded by the ACPI code in Dom0. Or
> else there wouldn't be a point to have an ACPI idle driver in Xen in the
> first place.
> 
> We should add custom (vendor specific) code to Xen only if there
> are clear advantages over the ACPI based approach, and so far
> the patch descriptions don't make clear what advantages there
> are (besides becoming independent of Dom0, which I'd consider
> marginal).
> 

I'll update the patches to explain why this is needed (aka, unreliable 
(PV dom0) or no passing (PVH dom0) of the ACPI tables back to Xen.

>> mwait has the CPUID_Fn00000005_EDX MSR but since we don't have a mwait
>> support for CC6, we can't use that.  There's another register we _might_
>> be able to use, but support for CC6 is AND'd with that and another
>> another register (we don't have access to). The register we'd read is
>> also RW.  So I'm not sure I trust it.
> 
> It's hard to believe that one can't find out whether HLT would enter
> only CC1 or eventually also CC6.
> 
> Jan
> 

There's a register, but it's AND'd with firmware for if C6 is enabled. 
Assuming it isn't touched, it should be able to determine if C6 is 
enabled or not by BIOS.  That leads to more code and the negative of not 
checking is system thinking it's using CC6 when it's really using CC1. 
It's also NDA'd so I'd have to get approval to use it (and then also put 
it in the public PPR).

Brian
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