[Xen-devel] [PATCH 1/2] x86/cpu/intel: Clear cache self-snoop capability in CPUs with known errata

[Jan Beulich <JBeulich@xxxxxxxx>]

From: Ricardo Neri <ricardo.neri-calderon@xxxxxxxxxxxxxxx>

Processors which have self-snooping capability can handle conflicting
memory type across CPUs by snooping its own cache. However, there exists
CPU models in which having conflicting memory types still leads to
unpredictable behavior, machine check errors, or hangs.

Clear this feature on affected CPUs to prevent its use.

Suggested-by: Alan Cox <alan.cox@xxxxxxxxx>
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@xxxxxxxxxxxxxxx>
[Linux commit 1e03bff3600101bd9158d005e4313132e55bdec8]

Strip Yonah - as per ark.intel.com it doesn't look to be 64-bit capable.
Call check_memory_type_self_snoop_errata() only on the boot CPU.

Requested-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>

--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -15,6 +15,32 @@
  #include "cpu.h"
  
  /*
+ * Processors which have self-snooping capability can handle conflicting
+ * memory type across CPUs by snooping its own cache. However, there exists
+ * CPU models in which having conflicting memory types still leads to
+ * unpredictable behavior, machine check errors, or hangs. Clear this
+ * feature to prevent its use on machines with known erratas.
+ */
+static void __init check_memory_type_self_snoop_errata(void)
+{
+       switch (boot_cpu_data.x86_model) {
+       case 0x0f: /* Merom */
+       case 0x16: /* Merom L */
+       case 0x17: /* Penryn */
+       case 0x1d: /* Dunnington */
+       case 0x1e: /* Nehalem */
+       case 0x1f: /* Auburndale / Havendale */
+       case 0x1a: /* Nehalem EP */
+       case 0x2e: /* Nehalem EX */
+       case 0x25: /* Westmere */
+       case 0x2c: /* Westmere EP */
+       case 0x2a: /* SandyBridge */
+               setup_clear_cpu_cap(X86_FEATURE_SS);
+               break;
+       }
+}
+
+/*
   * Set caps in expected_levelling_cap, probe a specific masking MSR, and set
   * caps in levelling_caps if it is found, or clobber the MSR index if missing.
   * If preset, reads the default value into msr_val.
@@ -256,8 +282,11 @@ static void early_init_intel(struct cpui
            (boot_cpu_data.x86_mask == 3 || boot_cpu_data.x86_mask == 4))
                paddr_bits = 36;
  
-       if (c == &boot_cpu_data)
+       if (c == &boot_cpu_data) {
+               check_memory_type_self_snoop_errata();
+
                intel_init_levelling();
+       }
  
        ctxt_switch_levelling(NULL);
  }

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