[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Xen-devel] [PATCH v3 08/14] AMD/IOMMU: introduce 128-bit IRTE non-guest-APIC IRTE format
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Jan Beulich <JBeulich@xxxxxxxx>
- Date: Tue, 23 Jul 2019 08:19:25 +0000
- Accept-language: en-US
- Arc-authentication-results: i=1; mx.microsoft.com 1;spf=pass smtp.mailfrom=suse.com;dmarc=pass action=none header.from=suse.com;dkim=pass header.d=suse.com;arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wM1962bKAm8ahbhg1jm2HCZQaBSbtEFmaCG8XqKSxWc=; b=c0+wuyaGv+SnEgiOnGt+HIAAyZzROB57jObHV7Kt5U7R2FnAZVDwwA4jzgUV6qoDbZianej4rPgixenxuKiTD0zP221KPf6a08dVh/CmstonxZ+IdUKdWgqmQfcFUyaNixRhorWOtW58FEqRjgWjrTUFaDqACkTNSVqm+eNOTd4yY3DFd/7VAxlO3KPuKKsmMiY3MVheOJz3VukPCQq8eR0xWVAKT7B3x9exxz3g8TcDTXOSUV/6HVaLSGO5zoooau/jPyPLZy9W8U+vReb6Q4JoapBEKfUzDSelpt3JzHU8V+L1ROGKnT2ptP1spvoRgE7f2AOkV7ueV1kb/3JtQg==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=U/IDNCtWzWBHUZkFgw3noa+6m5EEyELUp2wxcoFaCWuOx4qwtPCTKRDr0rBudx65EvQc/NowygDOR5HeQVryytsCufF6oGxneflMnj58I86ZQ3+o4EyQ5ycAtmqgsmHvZRgFmAOymbEfUucGWDZ4nJ3ZYX8SCV9aVTQPFsEIntyKrsLKCoAA/Itb4/LJJwYmaBGv/BslfdjLemngyeoyifl8HOLpjK96UiDVTvNpn076pEuW8n6R7TfChAU0dgTvB4txIoB91S6GTJiPhEhQb5AkDURyCZAJRDxn6ilRR0K17+P7bsjWM7hWgjrEaduQcSShpDfJLZ/6PHeZinvKGw==
- Authentication-results: spf=none (sender IP is ) smtp.mailfrom=JBeulich@xxxxxxxx;
- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, BrianWoods <brian.woods@xxxxxxx>, Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
- Delivery-date: Tue, 23 Jul 2019 08:19:51 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Thread-index: AQHVO/TlAPsnkpqPo0+X2y95y9fr6KbSNr9CgARDQ4CAADOwm4AAFvIAgAAMdA+AATWQAP//4BSA
- Thread-topic: Re:[PATCH v3 08/14] AMD/IOMMU: introduce 128-bit IRTE non-guest-APIC IRTE format
On 23.07.2019 10:13, Jan Beulich wrote:
> On 22.07.2019 17:43, Andrew Cooper wrote:
>> How would your argument change if the IOMMU was a real CPU running real
>> x86 code? Its interface to the rest of the system would be identical,
>> and in that case, it would obviously need an smp_{r,w}mb() pair for
>> correctness reasons. This is why smp_wmb() is the only appropriate
>> construct to use.
>
> It wouldn't change at all. What matters (as per above) is the
> understanding the OS has, i.e. what is being surfaced to it as CPU.
Oh, btw - I've got curious whether we could use Linux sources for
arbitration. What I found though is that they don't use any barrier
at all - see modify_irte_ga().
Jan
_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxxx
https://lists.xenproject.org/mailman/listinfo/xen-devel
|