[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 2/2] x86/iommu: avoid mapping the APIC configuration space for hwdom
Current code only prevents mapping the io-apic page into the guest physical memory map. Expand the range to be 0xFECx_xxxx as described in the Intel 3 Series Chipset Datasheet section 3.3.1 "APIC Configuration Space (FEC0_0000h–FECF_FFFFh)". AMD also lists this address range in the AMD SR5690 Databook, section 2.4.2 "Non-SB IOAPIC Support". Requested-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx> --- Cc: Jan Beulich <jbeulich@xxxxxxxx> Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> --- xen/drivers/passthrough/x86/iommu.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/xen/drivers/passthrough/x86/iommu.c b/xen/drivers/passthrough/x86/iommu.c index 88a87cf7a4..4dabfb2391 100644 --- a/xen/drivers/passthrough/x86/iommu.c +++ b/xen/drivers/passthrough/x86/iommu.c @@ -195,7 +195,7 @@ static bool __hwdom_init hwdom_iommu_map(const struct domain *d, unsigned long max_pfn) { mfn_t mfn = _mfn(pfn); - unsigned int i, type; + unsigned int type; /* * Set up 1:1 mapping for dom0. Default to include only conventional RAM @@ -229,10 +229,9 @@ static bool __hwdom_init hwdom_iommu_map(const struct domain *d, /* Check that it doesn't overlap with the Interrupt Address Range. */ if ( pfn >= 0xfee00 && pfn <= 0xfeeff ) return false; - /* ... or the IO-APIC */ - for ( i = 0; has_vioapic(d) && i < d->arch.hvm.nr_vioapics; i++ ) - if ( pfn == PFN_DOWN(domain_vioapic(d, i)->base_address) ) - return false; + /* ... or the APIC Configuration Space. */ + if ( pfn >= 0xfec00 && pfn <= 0xfecff ) + return false; /* * ... or the PCIe MCFG regions. * TODO: runtime added MMCFG regions are not checked to make sure they -- 2.20.1 (Apple Git-117) _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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