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Re: [Xen-devel] [PATCH 1/2] x86/iommu: avoid mapping the interrupt address range for hwdom
- To: Roger Pau Monne <roger.pau@xxxxxxxxxx>
- From: Jan Beulich <JBeulich@xxxxxxxx>
- Date: Tue, 23 Jul 2019 16:06:41 +0000
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- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Delivery-date: Tue, 23 Jul 2019 16:13:29 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
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- Thread-topic: [PATCH 1/2] x86/iommu: avoid mapping the interrupt address range for hwdom
On 23.07.2019 17:48, Roger Pau Monne wrote:
> Current code only prevent mapping the lapic page into the guest
> physical memory map. Expand the range to be 0xFEEx_xxxx as described
> in the Intel VTd specification section 3.13 "Handling Requests to
> Interrupt Address Range".
Right, and it being device side accesses that are of interest here,
the LAPIC address range (visible to the CPU only) shouldn't even
matter. Hence after some back and forth with myself I agree that
you remove the entire comment there.
> AMD also lists this address range in the AMD SR5690 Databook, section
> 2.4.4 "MSI Interrupt Handling and MSI to HT Interrupt Conversion".
Which raises the question about yet another patch to also exclude
the HT range.
> Requested-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
Jan
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