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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 1/3] x86/boot: Remove cached CPUID data from the trampoline
We have a cached cpuid_ext_features in the trampoline which is kept in sync by
various pieces of boot logic. This is complicated, and all it is actually
used for is to derive whether NX is safe to use.
Replace it with a canned value to load into EFER.
trampoline_setup() and efi_arch_cpu() now tweak trampoline_efer at the point
that they are stashing the main copy of CPUID data. Similarly,
early_init_intel() needs to tweak if it has re-enabled the use of NX.
This simplifies the AP boot and S3 resume paths by using trampoline_efer
directly, rather than locally turning FEATURE_NX into EFER_NX.
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
CC: Jan Beulich <JBeulich@xxxxxxxx>
CC: Wei Liu <wl@xxxxxxx>
CC: Roger Pau Monné <roger.pau@xxxxxxxxxx>
CC: Sergey Dyasli <sergey.dyasli@xxxxxxxxxx>
CC: Juergen Gross <jgross@xxxxxxxx>
---
xen/arch/x86/boot/head.S | 9 +++++++--
xen/arch/x86/boot/trampoline.S | 13 +++++--------
xen/arch/x86/boot/wakeup.S | 13 ++-----------
xen/arch/x86/cpu/common.c | 3 ---
xen/arch/x86/cpu/intel.c | 1 +
xen/arch/x86/efi/efi-boot.h | 8 +++++---
xen/include/asm-x86/processor.h | 2 +-
7 files changed, 21 insertions(+), 28 deletions(-)
diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S
index a1564b520b..77309e3c82 100644
--- a/xen/arch/x86/boot/head.S
+++ b/xen/arch/x86/boot/head.S
@@ -640,8 +640,13 @@ trampoline_setup:
jbe 1f
mov $0x80000001,%eax
cpuid
-1: mov %edx,sym_fs(cpuid_ext_features)
- mov
%edx,sym_fs(boot_cpu_data)+CPUINFO_FEATURE_OFFSET(X86_FEATURE_LM)
+1: mov %edx, sym_fs(boot_cpu_data) +
CPUINFO_FEATURE_OFFSET(X86_FEATURE_LM)
+
+ /* Check for NX. Adjust EFER setting if available. */
+ bt $cpufeat_bit(X86_FEATURE_NX), %edx
+ jnc 1f
+ orb $EFER_NX >> 8, 1 + sym_esi(trampoline_efer)
+1:
/* Check for availability of long mode. */
bt $cpufeat_bit(X86_FEATURE_LM),%edx
diff --git a/xen/arch/x86/boot/trampoline.S b/xen/arch/x86/boot/trampoline.S
index 870ec79a2d..26584493bb 100644
--- a/xen/arch/x86/boot/trampoline.S
+++ b/xen/arch/x86/boot/trampoline.S
@@ -88,8 +88,9 @@ trampoline_gdt:
GLOBAL(trampoline_misc_enable_off)
.quad 0
-GLOBAL(cpuid_ext_features)
- .long 0
+/* EFER OR-mask for boot paths. This gets adjusted with NX when available. */
+GLOBAL(trampoline_efer)
+ .long EFER_LME | EFER_SCE
GLOBAL(trampoline_xen_phys_start)
.long 0
@@ -132,14 +133,10 @@ trampoline_protmode_entry:
1:
/* Set up EFER (Extended Feature Enable Register). */
- mov bootsym_rel(cpuid_ext_features,4,%edi)
movl $MSR_EFER,%ecx
rdmsr
- or $EFER_LME|EFER_SCE,%eax /* Long Mode + SYSCALL/SYSRET */
- bt $cpufeat_bit(X86_FEATURE_NX),%edi /* No Execute? */
- jnc 1f
- btsl $_EFER_NX,%eax /* No Execute */
-1: wrmsr
+ or bootsym_rel(trampoline_efer, 4, %eax)
+ wrmsr
mov $(X86_CR0_PG | X86_CR0_AM | X86_CR0_WP | X86_CR0_NE |\
X86_CR0_ET | X86_CR0_MP | X86_CR0_PE), %eax
diff --git a/xen/arch/x86/boot/wakeup.S b/xen/arch/x86/boot/wakeup.S
index 25ec2fa32b..fc47721f43 100644
--- a/xen/arch/x86/boot/wakeup.S
+++ b/xen/arch/x86/boot/wakeup.S
@@ -131,20 +131,11 @@ wakeup_32:
wrmsr
1:
- /* Will cpuid feature change after resume? */
/* Set up EFER (Extended Feature Enable Register). */
- mov bootsym_rel(cpuid_ext_features,4,%edi)
- test $0x20100800,%edi /* SYSCALL/SYSRET, No Execute, Long Mode? */
- jz .Lskip_eferw
movl $MSR_EFER,%ecx
rdmsr
- btsl $_EFER_LME,%eax /* Long Mode */
- btsl $_EFER_SCE,%eax /* SYSCALL/SYSRET */
- btl $20,%edi /* No Execute? */
- jnc 1f
- btsl $_EFER_NX,%eax /* No Execute */
-1: wrmsr
-.Lskip_eferw:
+ or bootsym_rel(trampoline_efer, 4, %eax)
+ wrmsr
wbinvd
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 6c6bd63301..e5ad17d8d9 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -391,9 +391,6 @@ static void generic_identify(struct cpuinfo_x86 *c)
cpuid(0x80000001, &tmp, &tmp,
&c->x86_capability[cpufeat_word(X86_FEATURE_LAHF_LM)],
&c->x86_capability[cpufeat_word(X86_FEATURE_SYSCALL)]);
- if (c == &boot_cpu_data)
- bootsym(cpuid_ext_features) =
- c->x86_capability[cpufeat_word(X86_FEATURE_NX)];
if (c->extended_cpuid_level >= 0x80000004)
get_model_name(c); /* Default name */
diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 5356a6ae10..4d7324e4d0 100644
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -270,6 +270,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
if (disable) {
wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable);
bootsym(trampoline_misc_enable_off) |= disable;
+ bootsym(trampoline_efer) |= EFER_NX;
}
if (disable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID)
diff --git a/xen/arch/x86/efi/efi-boot.h b/xen/arch/x86/efi/efi-boot.h
index 940ce12706..cde193a771 100644
--- a/xen/arch/x86/efi/efi-boot.h
+++ b/xen/arch/x86/efi/efi-boot.h
@@ -238,7 +238,7 @@ static void __init noreturn efi_arch_post_exit_boot(void)
asm volatile("pushq $0\n\tpopfq");
rdmsrl(MSR_EFER, efer);
efer |= EFER_SCE;
- if ( cpuid_ext_features & cpufeat_mask(X86_FEATURE_NX) )
+ if ( cpu_has_nx )
efer |= EFER_NX;
wrmsrl(MSR_EFER, efer);
write_cr0(X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP |
@@ -640,9 +640,11 @@ static void __init efi_arch_cpu(void)
if ( (eax >> 16) == 0x8000 && eax > 0x80000000 )
{
- cpuid_ext_features = cpuid_edx(0x80000001);
boot_cpu_data.x86_capability[cpufeat_word(X86_FEATURE_SYSCALL)]
- = cpuid_ext_features;
+ = cpuid_edx(0x80000001);
+
+ if ( cpu_has_nx )
+ trampoline_efer |= EFER_NX;
}
}
diff --git a/xen/include/asm-x86/processor.h b/xen/include/asm-x86/processor.h
index b686156ea0..45d8f5117e 100644
--- a/xen/include/asm-x86/processor.h
+++ b/xen/include/asm-x86/processor.h
@@ -151,7 +151,7 @@ extern void ctxt_switch_levelling(const struct vcpu *next);
extern void (*ctxt_switch_masking)(const struct vcpu *next);
extern bool_t opt_cpu_info;
-extern u32 cpuid_ext_features;
+extern u32 trampoline_efer;
extern u64 trampoline_misc_enable_off;
/* Maximum width of physical addresses supported by the hardware. */
--
2.11.0
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