[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v3 5/6] x86/vpic: issue dpci EOI for cleared pins at ICW1

  • To: Jan Beulich <jbeulich@xxxxxxxx>
  • From: Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • Date: Wed, 27 Jan 2021 10:15:45 +0100
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rKB4PI/p3CL2RmYCwhEiYwHtz/HqvNcJujzCBD5UKlU=; b=f21BFkE1p++Bxdg+Z7UFAA4Q31YvCssB3j2TRts1O30N3lfN3fPLRuU9/jDQDnUz7Z7XNLRBFtBu2vxTt1iHESxPOUIjtxM7exeuIgdFYws81YreMrkrbZPMhC819yP/k+hnXfJto1qvVpb9PxYACBYvu3b+OFUjVIQTL3ReoFDhIE632Fju6JdTPdCWIlTUTUt/cKY+3xOGr1xGo9GLZkURc5HUNEjNVaOrv+DvsZz1fvn41Kv5xeqeokIpSOMLjv6IlG08itjmbEIPH8JLSQLzf2l/aNKBmwkysiyPxc/UQv4ibdWE7YJwxyk/dZ5DidesXJb4w5eXWn9YeN+7LA==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nuGPW7iMQORPM+7ymINyLO3rhALc4FGXZy5ElASqQae3DH3wCmUaP+4TEgxMF3d9slsQ27JDpEoW7mJu1a5WPYNLRLAgNebF0ZTew5R+daN/UPTWTMa2m1WXb/kc9SLQu4Fn1DnrkHs9mnTDV7CzrCeUas1ZP/B6YHWAf12AwHWyekKg0QfkHOJzgAc0Dpn5N5GaRKojZzMu9ZfzDG4N5XO5fkLermgO6bt8d9o9009oWVHdfRI4HPDrQ9p3hXMrJ84zuLZLhxdZpJ5IYDxwG91VFsrzUac1hZjuEQ7/A8UrDtrdoeeUB/FxNg6PN2qKMFqJMhqtNLGdo0dDmpVWrQ==
  • Authentication-results: esa1.hc3370-68.iphmx.com; dkim=pass (signature verified) header.i=@citrix.onmicrosoft.com
  • Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • Delivery-date: Wed, 27 Jan 2021 09:16:09 +0000
  • Ironport-sdr: I7/CW4kNaLeCyiX4y8moH6lCuJjn7/rQxTx8lTRBOpCkgPCd0inHAgQx9zF7e9XTs1B1uUrYax McVXW0ZtK7T7ma68XCria8dNGkSddeGOX45NOqTmkJQeFDwfv8WZZPZN8taY63P3DMOGmgVCMV q5slMSO3FLVZHHz+B+0HbB/i8lEFujdJz5hbwIp2TMhrV/+gDs+IjgQC/evJB1OxeK95FJGI7K cHZ2cy7HJOERJTqohVIASPPIj+4fW/GLYNyonNEMuf6PVELt8lD+c4cpFAvaf3CSV3T3obKD1p PW4=
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On Tue, Jan 26, 2021 at 05:57:49PM +0100, Jan Beulich wrote:
> On 26.01.2021 14:45, Roger Pau Monne wrote:
> > When pins are cleared from either ISR or IRR as part of the
> > initialization sequence forward the clearing of those pins to the dpci
> > EOI handler, as it is equivalent to an EOI. Not doing so can bring the
> > interrupt controller state out of sync with the dpci handling logic,
> > that expects a notification when a pin has been EOI'ed.
> > 
> > Fixes: 7b3cb5e5416 ('IRQ injection changes for HVM PCI passthru.')
> > Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
> As said before, under the assumption that the clearing of IRR
> and ISR that we do is correct, I agree with the change. I'd
> like to give it some time though before giving my R-b here, for
> the inquiry to hopefully get answered. After all there's still
> the possibility of us needing to instead squash that clearing
> (which then would seem to result in getting things in sync the
> other way around).

OK, let's wait a bit to see what Intel replies. I assume this would
qualify as a bugfix for getting it committed later?

Thanks, Roger.



Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.