[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 2/2] xen/pci: Gate all MSI code in common code with CONFIG_HAS_PCI_MSI
- To: Julien Grall <julien@xxxxxxx>
- From: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Date: Tue, 6 Apr 2021 16:59:26 +0200
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=W3G/7MkmYv1N15KpmZkYCQC+N+vTKHuoy/0b4UDlE60=; b=BEubVdQMTdNHQdvpae7gvRokUHup8+dnl/9UmJC7wUZ6ka8I4dOsWUTj4WVpz5OqjetF5X9eGvI/IyrWBY01tVGDhnBWw/fieRSwUyN53zRrCJ7tq83ySySHgs77H242CxxzrO8AT31db8rUv1cYOg+XygMqy/ebE4wqLsuoKpxJYfFv4+7/i8TjEwL9rwxau7C07XZF3U3NrILiY4deCFWxAZ9omwvfV0hndrZRlmNhCtb9QWjnkHC+EdaHu/qWVia/bD+IxYE08xu6Rh4dwXXdTnbIcn9vUIS/Pa5puwDXYkPyFFDcu6Ce54sb5nduWJfPRMjZOoJvmyjL7PCORg==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iczXN9TdJm17Eqo+xHL+MQ2evrLmgcBc8ZvKn9oyAep4/NFzIaMIAEYnYRmOeVqZK3bzY+GFv5d+4oK63ollkpTcN/xcjCjo9oqitr0mM0uedZ+CNJgpmqeT9wnwPV6XsXt6CURlEMTrSyctu3LOikt7r2UWh1CS9X6/UkrEEPsc3S0mzno/jVTVeQiECa0EKwdSpb84yY/MjOuYQ1QJQI8oP6xqpSzstb5C0xrPsLDPGYibaWijglld8OUpRIjQ4La8/msIhumpPo0J1dlNPd7nVkoZ8tgL12Km/qaKjjOzK/xVVY7oxpU0jyJs9igOl33d+wINONCJOGijQZZeGg==
- Authentication-results: esa5.hc3370-68.iphmx.com; dkim=pass (signature verified) header.i=@citrix.onmicrosoft.com
- Cc: Rahul Singh <rahul.singh@xxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxxx>, <bertrand.marquis@xxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Paul Durrant <paul@xxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, George Dunlap <george.dunlap@xxxxxxxxxx>, Ian Jackson <iwj@xxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Daniel De Graaf <dgdegra@xxxxxxxxxxxxx>
- Delivery-date: Tue, 06 Apr 2021 14:59:54 +0000
- Ironport-hdrordr: A9a23:0KRYAKNGhtRblcBcTxv155DYdL4zR+YMi2QD/1xtSBBTb8yTn9 2vmvNe7hPvlDMNQhgb9OyoEq+GXH/a6NpJ8ZAcVI3SOTXOlUmJCMVZ7YXkyyD9ACGWzIRg/I ppbqQWMrLNJHdgi8KS2meFOvIB5PXCz6yyn+fZyB5WPGNXQoVt9R1wBAreMmAefml7LKE0Hp ad+cZLzgDIERgqR/+2G2UfWKz7r8DL/aiMXTc9GxUl5AOS5AnYi4LSLh7w5HYjegIK+5gO2y zvkwv15qKs2svLsCP05ivowLl93PfkwttHLsSQhsYSMSWEsHfUWK1RH4eskRpwjOaz6Es7sN SkmWZdA+1Dr0n/U0vwgRzx1xLu2DwjgkWStmOwsD/YjuHSABcZYvAx4b5xQ1/ixGcL+OxY6u Zt2VmUspJGZCmw5BjV1pzzeDxB0navrWFKq591s1VvFbEwRZV2toIl8EZcAP47bVnHwbFiKu VoAc3GjcwmF2+yXjTctmlr9tSmQm4+KBeAWlQDocyYyVFt7QlE83c=
- Ironport-sdr: A0huk5ROgeOS/I2RyjX5UF2tYvt6K+l164S10nDGkN7H91zUpwFHgsDfGmLv87QjxnRU02Jjnh FUzFZVXUvSg4cvsPigjU9vC5vXpdU11KyXyaIcFReN78HGmt0BWMa8MsypxPEBaok5mUdi870w u03AMYY0P2wfUHKU9y79PxRVhozHmkbTA4LxHhB290lasT17AalxL8k1ZkUQvMv0nFU6+xYdOI 7mxRCnKN7EOswuWX6QTDYD4igO+y7uWriY1pkUvkG+iE6KSyripbgSK8ceJwMCsqZaoz33JR4v VGA=
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On Tue, Apr 06, 2021 at 03:30:01PM +0100, Julien Grall wrote:
> Hi Roger,
>
> On 06/04/2021 15:13, Roger Pau Monné wrote:
> > On Tue, Apr 06, 2021 at 12:39:11PM +0100, Rahul Singh wrote:
> > > MSI support is not implemented for ARM architecture but it is enabled
> > > for x86 architecture and referenced in common passthrough/pci.c code.
> > >
> > > Therefore introducing the new flag to gate the MSI code for ARM in
> > > common code to avoid compilation error when HAS_PCI is enabled for ARM.
> >
> > Is such option really interesting long term?
> >
> > IIRC PCI Express mandates MSI support, at which point I don't see much
> > value in being able to compile out the MSI support.
>
> I am pretty sure there are board out with PCI support but no MSI support.
> Anyway, even if the spec may mandate it...
>
> >
> > So while maybe helpful for Arm PCI efforts ATM, I'm not sure it
> > warrants a Kconfig option, I would rather see Arm introduce dummy
> > helpers for the missing functionality, even if unimplemented at the
> > moment.
>
> ... from my understanding, most of (if not all) the MSI code is not very
> useful on Arm when using the GICv3 ITS.
>
> The GICv3 ITS will do the isolation for you and therefore we should not need
> to keep track of the state at the vPCI level.
Right, but MSI has nothing to do with isolation, is just the
capability to setup interrupts from PCI devices. What about systems
without GICv3 ITS, is there an aim to support those also? (as from my
reading of your reply those would require more auditing of the MSI
accesses by the guests)
> So I think we want to be able to compile out the code if not used. That
> said, I think providing stub would be better to avoid multiple #ifdef in the
> same function.
I think providing stubs is the way to go, that should allow to remove
the unneeded code without having to explicitly drop MSI support. As
said before, I think it's fine to provide those unimplemented for Arm
ATM, can be filled later if there's more pressing PCI work to do
first.
Thanks, Roger.
|
