[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH] x86/spec-ctrl: Skip RSB overwriting when safe to do so


  • To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Tue, 24 Aug 2021 15:04:28 +0200
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yQl0WH6sI/Z9GXY2JJfMfkmze301t6nbON81sx+AnHQ=; b=HCEaOnIz9UujMNzJZBSrvI9jZkUU+p1++qP1rrCnoH4KXeAa9FJ2q1aLGiqg0QQWlQlBAYTvMRrZ1L90B1A8w3yvxrP2m64ekgfXGIj4fVq1c4e8FwXM91Xqa2FIVbzK4bNc2MlsjFWjcwzJMST9A7150nlNlGis8FLhLmo83MO8xN63/zawrAtzSZNouM5G/iNjuZWuoT0s7QQwysdaVpSPLxgNRLViPby6RlVdmopnVw3Vv5zvZU5i/6LKeuRGxpSiwh/bpPUhwJEiL0JNsWhBamZwcg36gEqI/YzgmnxnbZp07u+RNTA4a1/gv0X3eGa0iyhrDJKNcYt7jtoGKg==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=mRhijZsteHcFhHkeHvbxRICwrPwZ4V/Zhy4TkS48OkWLIXCyv9K/UC46EPZAYZHetZI2ZJXbkg7+GVMbG6gFyTCaLZ46C2OGeEMg6waBgjQ51rWvo+eGF5Xrgb0hlPbWSsX7U1ByjjnGDQCQsNilbo4Q78aXtBaRpnaUuvAI71uBQF3VrUJqEmMYrrsFX+bVPYqPeu77ghj13cvrPunnZAcpnQ064fnv7n58Yr25YP5SMDqUHvZewCGuXZ/+cExKqt2sNgmADJ56DlQmiiPAp0mLIMiPIPjFBmLXmLfxnrzzStacCpdEXitYV2RrnMLcN4nKA151MvbeAU0moDJDpQ==
  • Authentication-results: lists.xenproject.org; dkim=none (message not signed) header.d=none;lists.xenproject.org; dmarc=none action=none header.from=suse.com;
  • Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • Delivery-date: Tue, 24 Aug 2021 13:04:36 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 19.08.2021 18:26, Andrew Cooper wrote:
> In some configurations, it is safe to not overwrite the RSB on entry to Xen.
> Both Intel and AMD have guidelines in this area, because of the performance
> difference it makes for native kernels.

I don't think I've come across AMD's guidelines - would you happen to
have a pointer? Nevertheless ...

> A simple microperf test, measuring the amount of time a XENVER_version
> hypercall takes, shows the following improvements:
> 
>   KabyLake:     -13.9175% +/- 6.85387%
>   CoffeeLake-R:  -9.1183% +/- 5.04519%
>   Milan:        -17.7803% +/- 1.29808%
> 
> This is best case improvement, because no real workloads are making
> XENVER_version hypercalls in a tight loop.  However, this is the hypercall
> used by PV kernels to force evtchn delivery if one is pending, so it is a
> common hypercall to see, especially in dom0.
> 
> The avoidance of RSB-overwriting speeds up all interrupts, exceptions and
> system calls from PV or Xen context.  RSB-overwriting is still required on
> VMExit from HVM guests for now.
> 
> In terms of more realistic testing, LMBench in dom0 on an AMD Rome system
> shows improvements across the board, with the best improvement at 8% for
> simple syscall and simple write.
> 
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>

Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
albeit with one further remark / request:

> @@ -992,18 +1021,36 @@ void __init init_speculation_mitigations(void)
>          default_xen_spec_ctrl |= SPEC_CTRL_SSBD;
>  
>      /*
> -     * PV guests can poison the RSB to any virtual address from which
> -     * they can execute a call instruction.  This is necessarily outside
> -     * of the Xen supervisor mappings.
> +     * PV guests can create RSB entries for any linear address they control,
> +     * which are outside of Xen's mappings.
> +     *
> +     * SMEP inhibits speculation to any user mappings, so in principle it is
> +     * safe to not overwrite the RSB when SMEP is active.
> +     *
> +     * However, some caveats apply:
> +     *
> +     * 1) CALL instructions push the next sequential linear address into the
> +     *    RSB, meaning that there is a boundary case at the user=>supervisor
> +     *    split.  This can be compensated for by having an unmapped or NX
> +     *    page, or an instruction which halts speculation.
>       *
> -     * With SMEP enabled, the processor won't speculate into user mappings.
> -     * Therefore, in this case, we don't need to worry about poisoned entries
> -     * from 64bit PV guests.
> +     *    For Xen, the next sequential linear address is the start of M2P
> +     *    (mapped NX), or a zapped hole (unmapped).

IIUC you mean the compat M2P here - perhaps worth being explicit? I'm
also not sure why you use "zapped": Nothing can ever be mapped into
the non-canonical hole.

Jan




 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.