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Re: [PATCH v2 1/5] x86/cpuid: add CPUID flag for Extended Destination ID support
- To: David Woodhouse <dwmw2@xxxxxxxxxxxxx>
- From: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Date: Mon, 21 Feb 2022 10:36:10 +0100
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- Cc: Jan Beulich <jbeulich@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Mon, 21 Feb 2022 09:36:55 +0000
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- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On Sat, Feb 19, 2022 at 11:24:25AM -0000, David Woodhouse wrote:
>
>
> > /*
> > * With interrupt format set to 0 (non-remappable) bits 55:49 from the
> > * IO-APIC RTE and bits 11:5 from the MSI address can be used to store
> > * high bits for the Destination ID. This expands the Destination ID
> > * field from 8 to 15 bits, allowing to target APIC IDs up 32768.
> > */
>
> I am not keen on that wording because it doesn't seem to fully reflect the
> fact that the I/OAPIC is just a device to turn line interrupts into MSIs.
But that's an architecture implementation detail, I'm not sure I've
seen this written down explicitly in any specification.
> The values in bits 55:49 of the RTE *are* what go into bits 11:5 of the
> resulting MSI address. Perhaps make it more parenthetical to make it
> clearer that they are not independent... "bits 11:5 of the MSI address
> (which come from bits 55:49 of the I/OAPIC RTE)..."
That could be an option also, as long as it's clear to which bits of
the IO-APIC RTE this affects.
Thanks, Roger.
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