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Re: [PATCH] x86/spec-ctrl: More MSR_ARCH_CAPS enumerations
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Date: Mon, 13 Jun 2022 09:40:09 +0200
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- Cc: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Jan Beulich <JBeulich@xxxxxxxx>, Wei Liu <wl@xxxxxxx>
- Delivery-date: Mon, 13 Jun 2022 07:40:27 +0000
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- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On Fri, Jun 10, 2022 at 05:00:50PM +0100, Andrew Cooper wrote:
> https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/data-operand-independent-timing-isa-guidance.html
> https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/running-average-power-limit-energy-reporting.html
>
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> ---
> CC: Jan Beulich <JBeulich@xxxxxxxx>
> CC: Roger Pau Monné <roger.pau@xxxxxxxxxx>
> CC: Wei Liu <wl@xxxxxxx>
>
> The SDM also lists
>
> #define ARCH_CAPS_OVERCLOCKING_STATUS (_AC(1, ULL) << 23)
>
> but I've got no idea what this is, nor the index of MSR_OVERCLOCKING_STATUS
> which is the thing allegedly enumerated by this.
> ---
> xen/arch/x86/include/asm/msr-index.h | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/xen/arch/x86/include/asm/msr-index.h
> b/xen/arch/x86/include/asm/msr-index.h
> index 6c250bfcadad..781584953654 100644
> --- a/xen/arch/x86/include/asm/msr-index.h
> +++ b/xen/arch/x86/include/asm/msr-index.h
> @@ -51,6 +51,9 @@
> #define PPIN_ENABLE (_AC(1, ULL) << 1)
> #define MSR_PPIN 0x0000004f
>
> +#define MSR_MISC_PACKAGE_CTRL 0x000000bc
Not sure it's worth it, but Intel names this MISC_PACKAGE_CTLS rather
than CTRL, same with the bit below in ARCH_CAPABILITIES.
Thanks, Roger.
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