[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v2 1/2] x86/spec-ctrl: Only adjust MSR_SPEC_CTRL for idle with legacy IBRS


  • To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • From: Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • Date: Thu, 30 Jun 2022 18:39:52 +0200
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=9JDgQkCJ8TUJba+XuzjE+dL45nQdMlCa1F+//oCj2HA=; b=U2munDzErxkySHN7k1Wuk+y1T/X6agMYEQvHrR5EJh+wV8Cli76C9+fc/2rY2Q9oh4Ygrnd/dHDzK1i09FOH8eIqBhNAAlep1DWEjSglMlqRP0O+BevDs/hntdQSVubpzdEqzV6RPRbgQM9Oys5wMkucRLBa5wEsDvApV1TICGp1xjjyQcMbgK7ziocuFyYel08BtEH2MNsmQ6X83EIjL/lqledj9eeZRIRqpZGPFxvHl9mRfJcFta8TE0fWvyAiRu4tIZZnDj4ptiyG3U/zmJl6FxVJ3A/SGh8VFEUxO08al6bbwaNDvM4mxc/pGLbSUoTU+SNuy1nILKwjCpNeKQ==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jxO9Ygnf9M4rb8QYwVU4tIDrWtfPzfXh7kDAALXIYAyOQdoOHMkRtAhTOJkEOybKuP6hmjF3/MAGckrmCn2qaR7k/GGuVKvsWYe9Il10+ySVEoJFnBzu8qI1EI6Mta1AlkNmHVhQ2EX43g5WcfcPKAZXBBzdfgfLICf/Nowcl+Z1IpOwWBSJKMlBqjDNSEs+RyU8l9BDC/nihxkToBJuUmlCurKMt2FNPCdNQfhTM4tz56Hg4105xxmxEkkJC0O2Q9qFry+F9+/1KKnmWSCOw1ju7s802jhdh7FEkIfNC/NZ9j6FYdifHGJtzVjAG0tzZSa89JLhh2ZZ0aXGISStqQ==
  • Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com;
  • Cc: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Jan Beulich <JBeulich@xxxxxxxx>, Wei Liu <wl@xxxxxxx>
  • Delivery-date: Thu, 30 Jun 2022 16:40:02 +0000
  • Ironport-data: A9a23:oW28M65BogXUBpe0tk8PcAxRtEzGchMFZxGqfqrLsTDasY5as4F+v mMaWmjUP/eDZWDwfI91O4m09kkE7JXUmIBkGwBsrnwyHi5G8cbLO4+Ufxz6V8+wwmwvb67FA +E2MISowBUcFyeEzvuVGuG96yE6j8lkf5KkYAL+EnkZqTRMFWFw03qPp8Zj2tQy2YbiW1vX0 T/Pi5a31GGNimYc3l08s8pvmDs31BglkGpF1rCWTakjUG72zxH5PrpGTU2CByKQrr1vNvy7X 47+IISRpQs1yfuP5uSNyd4XemVSKlLb0JPnZnB+A8BOiTAazsA+PzpS2FPxpi67hh3Q9+2dx umhurSRWxh2DPPlwdgZaCh7TCQlL4t856/udC3XXcy7lyUqclPK6tA3VAQTAtdd/ex6R2ZT6 fYfNTYBKAiZgP67y666Te8qgdk/KM7sP8UUvXQIITPxVK56B8ycBfiXo4YAgl/chegXdRraT 9AeZjd1KgzJfjVEO0sNCYJ4l+Ct7pX6W2IH8wLJ9Pppi4TV5Fxw1+bVbPDZQcS1HIZOrBiZr UHH3GusV3n2M/Tak1Jp6EmEluLJ2C/2Ro8WPLm57eJxxk2ewHQJDx8bXkf9puO24maccd9CL 00f+gI1sLM/skesS7HVQBmQsHOC+BkGVLJt//YS7QiMzu/R/FyfD21dFjpZMoV+6okxWCAg0 UKPk5XxHztzvbaJSHWbsLCJsTe1PitTJmgHDcMZcTY4DxDYiNlbpnryohxLSsZZUvWd9enM/ g23
  • Ironport-hdrordr: A9a23:BGSG6qE8dQaBHpTYpLqFc5HXdLJyesId70hD6qkvc3Fom52j/f xGws5x6faVslkssb8b6LW90Y27MAvhHPlOkPIs1NaZLXDbUQ6TQL2KgrGD/9SNIVycygcZ79 YbT0EcMqyOMbEZt7ec3ODQKb9Jrri6GeKT9IHjJh9WPH1XgspbnmNE42igYy9LrF4sP+tFKH PQ3LswmxOQPVAsKuirDHgMWObO4/XNiZLdeBYDQzoq8hOHgz+E4KPzV0Hw5GZXbxp/hZMZtU TVmQ3w4auu99m91x/nzmfWq7BbgsHoxNdvDNGFzuIVNjLvoAC1Y5kJYczKgBkF5MWUrHo6mt jFpBkte+x19nPqZ2mw5SDg3gHxuQxenkPK+Bu9uz/OsMb5TDU1B45qnoRCaCbU7EImoZVVzL 9L93jxjesaMTrw2ADGo/TYXRBjkUS55VA4l/QIsnBZWYwCLJdMsI0k+l9PGptoJlO21GkeKp ghMCjg3ocWTbvDBEqp/lWHgebcFEjbJy32DXTr4aeuontrdHMQ9Tpr+CVQpAZDyHsHceg02w 31CNUXqFhwdL5nUUtcPpZ0fSLlMB27fTv8dESvHH/AKIYrf1rwlr+f2sRH2AjtQu1C8KcP
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On Wed, Jun 29, 2022 at 07:45:07PM +0100, Andrew Cooper wrote:
> Back at the time of the original Spectre-v2 fixes, it was recommended to clear
> MSR_SPEC_CTRL when going idle.  This is because of the side effects on the
> sibling thread caused by the microcode IBRS and STIBP implementations which
> were retrofitted to existing CPUs.
> 
> However, there are no relevant cross-thread impacts for the hardware
> IBRS/STIBP implementations, so this logic should not be used on Intel CPUs
> supporting eIBRS, or any AMD CPUs; doing so only adds unnecessary latency to
> the idle path.
> 
> Furthermore, there's no point playing with MSR_SPEC_CTRL in the idle paths if
> SMT is disabled for other reasons.
> 
> Fixes: 8d03080d2a33 ("x86/spec-ctrl: Cease using thunk=lfence on AMD")
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>

Reviewed-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>

Thanks, Roger.



 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.