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Re: [PATCH 02/11] x86emul: handle AVX512-FP16 insns encoded in 0f3a opcode map


  • To: Andrew Cooper <Andrew.Cooper3@xxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Thu, 11 Aug 2022 08:11:56 +0200
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  • Cc: Wei Liu <wl@xxxxxxx>, Roger Pau Monne <roger.pau@xxxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • Delivery-date: Thu, 11 Aug 2022 06:12:32 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 10.08.2022 19:03, Andrew Cooper wrote:
> On 15/06/2022 11:27, Jan Beulich wrote:
>> In order to re-use (also in subsequent patches) existing code and tables
>> as much as possible, simply introduce a new boolean field in emulator
>> state indicating whether an insn is one with a half-precision source.
>> Everything else then follows "naturally".
> 
> This is slightly misleading.  What you mean is it has an FP16 source, I
> think?
> 
> There are non-FP16 instructions which have half-precision inputs, like
> the F16C group.

I don't see the difference - both use the same floating point format.
Whether you call it FP16 or half-precision is imo secondary. In fact the
new boolean might be usable for the F16C insns as well, if we wanted to.

>> --- a/tools/tests/x86_emulator/x86-emulate.h
>> +++ b/tools/tests/x86_emulator/x86-emulate.h
>> @@ -182,6 +182,7 @@ void wrpkru(unsigned int val);
>>  #define cpu_has_avx512_4fmaps (cp.feat.avx512_4fmaps && xcr0_mask(0xe6))
>>  #define cpu_has_avx512_vp2intersect (cp.feat.avx512_vp2intersect && 
>> xcr0_mask(0xe6))
>>  #define cpu_has_serialize  cp.feat.serialize
>> +#define cpu_has_avx512_fp16 (cp.feat.avx512_fp16 && xcr0_mask(0xe6))
>>  #define cpu_has_avx_vnni   (cp.feat.avx_vnni && xcr0_mask(6))
>>  #define cpu_has_avx512_bf16 (cp.feat.avx512_bf16 && xcr0_mask(0xe6))
>>  
>> --- a/xen/arch/x86/x86_emulate/decode.c
>> +++ b/xen/arch/x86/x86_emulate/decode.c
>> @@ -518,6 +518,7 @@ static const struct ext0f3a_table {
>>      [0x7a ... 0x7b] = { .simd_size = simd_scalar_opc, .four_op = 1 },
>>      [0x7c ... 0x7d] = { .simd_size = simd_packed_fp, .four_op = 1 },
>>      [0x7e ... 0x7f] = { .simd_size = simd_scalar_opc, .four_op = 1 },
>> +    [0xc2] = { .simd_size = simd_any_fp, .d8s = d8s_vl },
> 
> This is a new instruction, isn't it?

Well, its the analogue of the space-0F encoded VCMPP{S,D} with the same
major opcode. I have to admit that it's unclear to me why you're asking.

Jan



 


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