[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [RFC PATCH v1 03/12] Arm: GICv3: Enable vreg_reg64_* macros for AArch32
- To: Julien Grall <julien@xxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- From: Ayan Kumar Halder <ayankuma@xxxxxxx>
- Date: Tue, 25 Oct 2022 16:59:39 +0100
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TCQKQzD5HwavRhiH24ue/a+nJT22VYAuQrHCwGp/X5o=; b=koOC/5iLi2q8zjCJNTNKC22ZDdCJnz00YEFGGSMM61g+UayE1C8p6BpVs1CwaVufGK3Nyq8klrqQSvGqRe4LzTyZlGMOB7jjuulbHC/CV/gYiAS5AIcB9I93Ujd+S4MZgnEqiXm2GgCbnR6pNjAvg7hpWI+ND7GvMgke72BnHqxgA4A+rCI/xfmJmlEhMMcx5A58W7phQwMT/5oBh9PnfZwuYtjpmrDQNwBuU3CtP+GTCIbYKGZEmSxztt6q4fPRO4lmspj7InhRqtMTKVzMQUY/xchClQNVYeDlqRW/Ss+lZ1SWTfaq8gPtb9ahKat+gcleiY9Uf5RUffG+j1p+0g==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TpeVi+50FmrkXED0Rn71IsDBCpmYLonoHRSFOomF0pBEruzOpjXS1nZ8IlXeBKcAMoKqPDKFSVEqdcVCkUXNLpA8Yg3phxq0m/FTm3Ea/SuduGvKpBA9sHr/M3Wu7By5lbjfxsB3pLo/gjALYIvLo7ESNu3xaNQ9FkhQQkJRYhlwuvYQTPhqtGbD8nZBh+C2Idy/eM1L4l6rKKLJa/O+gOYmCk47Odcr+gCz6k75jsqnerJA6cE+LWvP7+gE5R/P8SsqqaRbk5lYjylKWqWYbKz39niXY93dPGr0Q/9FEJl898weDQCtER5+lhx/w5hPJQQcV1rkOdmtIR/C7xAGBw==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com;
- Cc: sstabellini@xxxxxxxxxx, stefanos@xxxxxxxxxx, Volodymyr_Babchuk@xxxxxxxx, bertrand.marquis@xxxxxxx
- Delivery-date: Tue, 25 Oct 2022 15:59:55 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
Hi Julien,
static inline void vreg_reg##sz##_update(uint##sz##_t *reg,
register_t val,
const mmio_info_t *info)
{
uint##sz##_t tmp = *reg;
Drop this as we don't use tmp.
uint##sz##_t mask = VREG_REG_MASK(info->dabt.size);
unsigned int offset = info->gap & (offsetmask);
int shift = offset * 8;
*reg &= ~(mask << shift);
*reg |= ((uint##sz##_t)val & mask) << shift;
}
I think this is correct. Except for an improvement (as above).
Also, we will always keep this defined for both Arm32 and Arm64
VREG_REG_HELPERS(32, 0x3);
VREG_REG_HELPERS(64, 0x7);
- Ayan
|
