[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
RE: [PATCH for-4.17 v3 1/2] amd/virt_ssbd: set SSBD at vCPU context switch
- To: Roger Pau Monne <roger.pau@xxxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Henry Wang <Henry.Wang@xxxxxxx>
- Date: Thu, 3 Nov 2022 17:06:19 +0000
- Accept-language: zh-CN, en-US
- Arc-authentication-results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com])
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
- Arc-message-signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=09TC2OjTAstvwX+aOcOTzRe5uVb8e6TNwkmQHhTATSo=; b=IId4kwDYsAgmjwgOUZyv/ye3pRSfzQY/gCnE0pDDxUj+U/XW/EeE8+sM8gJ3cdX339Bf2mRQSnUxdhMGJJ6ngmBqLrX4mD/a1Pg56FjS1x/lPH3pSA4RV1CRVo82WBra6YSibYYxztuE9clp/96xot7POl0rSCFXw5DD5Ptl9XpD4c2nQ7StFqZg1ZkmbXiKztxdA5RGYOuWbjudetxoMcAE1r4bfMJ7HTeD4jPph5aPzdvWYufYH+x+zMOcm1e9Vgk12r+LQP1OWgvymQkvB//Vvi6WnYTKX4rQd00sJh6iXTVTuXxTN/U+RZIycNHd/Plg+KMJWbVfIBTCaZxYeQ==
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=09TC2OjTAstvwX+aOcOTzRe5uVb8e6TNwkmQHhTATSo=; b=lOxaB0qY0hNS/aJpdShkzoPpDOJ5bJ9w0oBxKyTNgImT860ujZL5msSL8iQsPduyYLH9TmHxzQ9CLde4dAzSLpJ9U701tszrLQTg65Q7AwExJjtUXcSLGV6EzRLXjvCLZ/iLDcGbzO1Gl9wFmu3au2GwxaJ4fiqo2PH8Ceqn0GZqioAvywiBcyJrVWm0o8ULrZ/ldswFyTxKB1ZRe59Ijo2TLS0N6UnilXOOCsWSh0EQK1ErUIST2OplC0wja0VfNqYd9P4ZcXbgzRK/oEu2kI7bavWIuheHnIFmfCbWOuQwWmaNcxwqh939d6Z2PBTYOMrPR2FXNeurUzAx0xrsXw==
- Arc-seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=ER6Ov0XGtPvYVOVz1m8flvuystqaPNNV0/gG1VJduZmlr1h7GJuO4Pgzo5FA+KWvd2+HvYkJLZqFm2efV/6awBlG7UbE4QVqAwLChe5oaJ92DKDorDAQr+DozB5B5DyMmrYXHvzm8d3G+/cW/Ki6qjggaP1+vT1J0RjqDhaKdaAQvc8BLhyERSYbCKi52DEc6MV7PFZ4l13Mvq5yd/81p1wpCfK2+oQyqiV6MJCZxqt3JVM+P0ceMUY09SOnRWLzyNgrQ2miM6Vxv5ym2Q7yVSrGXzHGeOoTzm8uVs+BGVn/ZDFe39w/F90+fNUpvOjKx3BwYMrtp0ZB+qwWx+dxHA==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VJNgC3XYTeXFjHz1EHxrRgH7Syv/ngFoKues6+V6L1Zna+4VASOZrLapIeKO3i7EXy6thZ2UbjRHYxe58IKdAh1Al6gVyfQFQvLWpt8AH+ZSXXzR5PEI0YX9Wl0SyB8skosUAYB5S9Dlw1K/sBkxBpLrfU2iIzj7Qm5chpK4zY26E5BSwuHSLX0ejTd/BxtNzcqyPhRSRE0uW2mWfBxi3/DtpiZH9CKrYEUwxnv+BVYhasktbgsisCZw53ZOwIDJRFwrr/xXg7pJ5nKCJQydx20fWGaXoP9fYPBrWPN+C1led6RbuRsES6o7eYnPtkxlfms2QhCxmIhcx3fXt+XvdQ==
- Authentication-results-original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, George Dunlap <george.dunlap@xxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Julien Grall <julien@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
- Delivery-date: Thu, 03 Nov 2022 17:06:34 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Nodisclaimer: true
- Original-authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Thread-index: AQHY76ZET1O4McAMZk+SDG8R2oR8564tbbLA
- Thread-topic: [PATCH for-4.17 v3 1/2] amd/virt_ssbd: set SSBD at vCPU context switch
Hi Roger,
> -----Original Message-----
> From: Roger Pau Monne <roger.pau@xxxxxxxxxx>
> Subject: [PATCH for-4.17 v3 1/2] amd/virt_ssbd: set SSBD at vCPU context
> switch
>
> The current logic for AMD SSBD context switches it on every
> vm{entry,exit} if the Xen and guest selections don't match. This is
> expensive when not using SPEC_CTRL, and hence should be avoided as
> much as possible.
>
> When SSBD is not being set from SPEC_CTRL on AMD don't context switch
> at vm{entry,exit} and instead only context switch SSBD when switching
> vCPUs. This has the side effect of running Xen code with the guest
> selection of SSBD, the documentation is updated to note this behavior.
> Also note that then when `ssbd` is selected on the command line guest
> SSBD selection will not have an effect, and the hypervisor will run
> with SSBD unconditionally enabled when not using SPEC_CTRL itself.
>
> This fixes an issue with running C code in a GIF=0 region, that's
> problematic when using UBSAN or other instrumentation techniques.
>
> As a result of no longer running the code to set SSBD in a GIF=0
> region the locking of amd_set_legacy_ssbd() can be done using normal
> spinlocks, and some more checks can be added to assure it works as
> intended.
>
> Finally it's also worth noticing that since the guest SSBD selection
> is no longer set on vmentry the VIRT_SPEC_MSR handling needs to
> propagate the value to the hardware as part of handling the wrmsr.
>
> Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>
Thanks for respinning the patch!
Release-acked-by: Henry Wang <Henry.Wang@xxxxxxx>
Kind regards,
Henry
|
