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Re: [PATCH 2/2] x86/vmx: Support for CPUs without model-specific LBR
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Tue, 10 Jan 2023 17:28:50 +0100
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- Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Jun Nakajima <jun.nakajima@xxxxxxxxx>, Kevin Tian <kevin.tian@xxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Tue, 10 Jan 2023 16:28:57 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 09.01.2023 13:08, Andrew Cooper wrote:
> Ice Lake (server at least) has both Arch LBR and model-specific LBR. Sapphire
> Rapids does not have model-specific LBR at all. I.e. On SPR and later,
> model_specific_lbr will always be NULL, so we must make changes to avoid
> reliably hitting the domain_crash().
>
> The Arch LBR spec states that CPUs without model-specific LBR implement
> MSR_DBG_CTL.LBR by discarding writes and always returning 0.
>
> Do this for any CPU for which we lack model-specific LBR information.
>
> Adjust the now-stale comment, now that the Arch LBR spec has created a way to
> signal "no model specific LBR" to guests.
>
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
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