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RE: [PATCH v4 08/14] xen/arm32: head: Introduce an helper to flush the TLBs
- To: Julien Grall <julien@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Henry Wang <Henry.Wang@xxxxxxx>
- Date: Sat, 14 Jan 2023 02:16:32 +0000
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- Cc: Luca Fancellu <Luca.Fancellu@xxxxxxx>, Julien Grall <jgrall@xxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
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- Thread-topic: [PATCH v4 08/14] xen/arm32: head: Introduce an helper to flush the TLBs
Hi Julien,
> -----Original Message-----
> Subject: [PATCH v4 08/14] xen/arm32: head: Introduce an helper to flush the
> TLBs
>
> From: Julien Grall <jgrall@xxxxxxxxxx>
>
> The sequence for flushing the TLBs is 4 instruction long and often
> requires an explanation how it works.
>
> So create a helper and use it in the boot code (switch_ttbr() is left
> alone until we decide the semantic of the call).
>
> Note that in secondary_switched, we were also flushing the instruction
> cache and branch predictor. Neither of them was necessary because:
> * We are only supporting IVIPT cache on arm32, so the instruction
> cache flush is only necessary when executable code is modified.
> None of the boot code is doing that.
> * The instruction cache is not invalidated and misprediction is not
> a problem at boot.
>
> Signed-off-by: Julien Grall <jgrall@xxxxxxxxxx>
Reviewed-by: Henry Wang <Henry.Wang@xxxxxxx>
I've also tested this patch on FVP in arm32 execution mode, and
this patch is good, so:
Tested-by: Henry Wang <Henry.Wang@xxxxxxx>
Kind regards,
Henry
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