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Re: [PATCH] x86: extend coverage of HLE "bad page" workaround
- To: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Tue, 21 Mar 2023 16:51:43 +0100
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- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
- Delivery-date: Tue, 21 Mar 2023 15:51:50 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 21.03.2023 15:42, Roger Pau Monné wrote:
> On Tue, May 26, 2020 at 08:49:52AM +0200, Jan Beulich wrote:
>> Respective Core Gen10 processor lines are affected, too.
>>
>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
>>
>> --- a/xen/arch/x86/mm.c
>> +++ b/xen/arch/x86/mm.c
>> @@ -6045,6 +6045,8 @@ const struct platform_bad_page *__init g
>> case 0x000506e0: /* errata SKL167 / SKW159 */
>> case 0x000806e0: /* erratum KBL??? */
>> case 0x000906e0: /* errata KBL??? / KBW114 / CFW103 */
>> + case 0x000a0650: /* erratum Core Gen10 U/H/S 101 */
>> + case 0x000a0660: /* erratum Core Gen10 U/H/S 101 */
>
> I think this is errata CML101, I would add that at the end of the
> comment.
Indeed in the current version of the document CML prefix exist. The older
document I've been looking at has no such letter acronyms in front of the
errata numbers. I can certainly update.
> Also you seem to be missing the '806ec' model (806e0 case)? (listed as
> 'U 4+2 V1')
Isn't that pre-existing (see 2nd line of context above)?
Jan
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