[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [XEN v4 07/11] xen/arm: Introduce choice to enable 64/32 bit physical addressing


  • To: Ayan Kumar Halder <ayankuma@xxxxxxx>, Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Wed, 22 Mar 2023 07:59:29 +0100
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Azqc6YVWAQyr/PmMldzzABVgRpIjCYiYyTdO7M0cbDQ=; b=FaYJmGSMVmdV5eDvo7lb6zjQRAZWrB1Fml8aNZn7Cfpno/U6fs9gGPuYTNiyx4ImifrWFb88kbHhxVgSgmpHESzsRkUf9OBD7uE997nrdLu7Cy5P4xdzkqH6AK+S29by2xzreIZI47+i1WKCccvuitzVqMVo7+TnsZ9tzHQ4OGh+ZLdwiMJsfc6YXLVTDCvtfL+tFaQK+x+nKBq9G4UkXAheWYTYUNny2FoWnhT8XHo1aOZ7sZiJxZX2FVITmYKr58QvcQI6cGEu0Q5PQS5UOqlZ96N/HoMg1I32CzjesmKyZ5SYxyFK0NcwniVu3olZz1+nWlE+yDWjOmt3jKLUKw==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PAr8rne+VDXuGC9ei52Hw/uY11qhwscAeYNg3VfAFV+ynhzw680GVltxK00D3UsN737M90QomKjAPCkLvwz9K+UQarsX4/YZdSfyqVsf3zwnIH6fRTf5dgqUPRRlic8V5A6MwVW976qL5OH4pMrHAKv+DK6G3TcVygSkaAYSnI7QRWbViKIxfM0tKgLe3cud3Irtr7klCsbEql3y9ONn6PbOz2LEAFleQi0OwVYmPSuSQqWLVzkwzE0uPi84+rqkD5eeyyH8Q3if+z2HrSOwmlQSGVaZWIxlQKA1JuYqYkQ4mtCZ9Mnd3rXybL3rG3Bo6PxqpkbXi+U9z0mJ6lO/xw==
  • Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com;
  • Cc: sstabellini@xxxxxxxxxx, stefano.stabellini@xxxxxxx, julien@xxxxxxx, Volodymyr_Babchuk@xxxxxxxx, bertrand.marquis@xxxxxxx, andrew.cooper3@xxxxxxxxxx, george.dunlap@xxxxxxxxxx, wl@xxxxxxx, rahul.singh@xxxxxxx, xen-devel@xxxxxxxxxxxxxxxxxxxx
  • Delivery-date: Wed, 22 Mar 2023 06:59:42 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 21.03.2023 19:33, Ayan Kumar Halder wrote:
> On 21/03/2023 16:53, Jan Beulich wrote:
>> On 21.03.2023 17:15, Ayan Kumar Halder wrote:
>>> On 21/03/2023 14:22, Jan Beulich wrote:
>>>> (Using "unsigned long" for a 32-bit paddr_t is of
>>>> course suspicious as well - this ought to be uint32_t.)
>>> The problem with using uint32_t for paddr_t is that there are instances
>>> where the paddr_t is modified with PAGE_MASK or PAGE_ALIGN.
>>>
>>> For eg , handle_passthrough_prop()
>>>
>>>               printk(XENLOG_ERR "Unable to permit to dom%d access to"
>>>                      " 0x%"PRIpaddr" - 0x%"PRIpaddr"\n",
>>>                      kinfo->d->domain_id,
>>>                      mstart & PAGE_MASK, PAGE_ALIGN(mstart + size) - 1);
>>>
>>> And in xen/include/xen/page-size.h,
>>>
>>> #define PAGE_SIZE           (_AC(1,L) << PAGE_SHIFT)
>>> #define PAGE_MASK           (~(PAGE_SIZE-1))
>>>
>>> Thus, the resulting types are unsigned long. This cannot be printed
>>> using %u for PRIpaddr.
>> Is there anything wrong with making PAGE_SIZE expand to (1 << PAGE_SHIFT)
>> when physical addresses are only 32 bits wide?
> 
> I don't have a strong objection except that this is similar to what 
> linux is doing today.
> 
> https://elixir.bootlin.com/linux/latest/source/arch/arm/include/asm/page.h#L12
> 
>>
>>> I remember some discussion (or comment) that the physical addresses
>>> should be represented using 'unsigned long'.
>> A reference would be helpful.
> 
> https://lists.xenproject.org/archives/html/xen-devel/2023-02/msg00305.html

I see. I guess this will be okay as long as only 32-bit arches elect to
use 32-bit physical addresses. Maybe there should be a BUILD_BUG_ON()
somewhere, accompanied by a suitable comment?

Jan



 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.