[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2 1/2] restrict concept of pIRQ to x86
- To: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Thu, 4 May 2023 10:21:23 +0200
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=aI0/JyEON9kCkhqTyTPi7ggRbwp5JhYQG2jo6txVfvQ=; b=h/0hiF3Jdjz5YAuen/QLsYPpCzLbDT1R/vFWhY20TSJvDuMC9xPiGIk8jBiieztAOSmAFCiyvfTplIqn0fPUaXTbpdhAErZIocPPqJq6VFHIK74ETQtodEJPo+0cGmN18nlq6CaC0YZ9IieOQSWGg54rswrBXLay94N9zgizjfxWDgdvFs5me0P7SWvdD3igYij11b26cug+2TAa902S51OreP97fMYlclotRM0hX8JcXM9u5zSpwJBbaAp6rN8m6FmlNkJEwNw1XVCmffg3NMSFC+5d308PC1Mp23de6UwxNDvrtLsFaBHqbHkkJB1nvuZXc8VB3z5+1urPqfLdKg==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dzZ7YQWEJzZZfabhrbsKP041Xp5luhcZjaLYohDTM1Mkxrc/P/+JX/vwsLwyu7Oy2ke3gnKmcaxcSscIj5qQBcAu6dvwxBKIi4lZYYX4MGX/g4kyoCDs0ono0QFRjbvBICd5JEDyj1tmj9pLuq+UCLkxU2/29k4A8bAPugjHYF13watgpav5+2AnhVLC8GLVd8RmYzVPzMWu7TkS9nd519DBqrkPiCi04QqHHmKMdxsKLoZeGuYS3Qs6Ah3MZyY86O0osBqd6B/jlDKpukKKrXBcwIGDcH/jjNtDtePu642bBpBYyE4dAp1jhDKAv5jhHsx1rjXWOAwI0rdFSKOYOg==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com;
- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, George Dunlap <george.dunlap@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Volodymyr Babchuk <volodymyr_babchuk@xxxxxxxx>
- Delivery-date: Thu, 04 May 2023 08:21:35 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 04.05.2023 10:13, Roger Pau Monné wrote:
> On Thu, May 04, 2023 at 09:50:27AM +0200, Jan Beulich wrote:
>> On 04.05.2023 09:44, Roger Pau Monné wrote:
>>> On Wed, May 03, 2023 at 05:33:05PM +0200, Jan Beulich wrote:
>>>> --- a/xen/include/xen/sched.h
>>>> +++ b/xen/include/xen/sched.h
>>>> @@ -438,12 +438,14 @@ struct domain
>>>>
>>>> struct grant_table *grant_table;
>>>>
>>>> +#ifdef CONFIG_HAS_PIRQ
>>>> /*
>>>> * Interrupt to event-channel mappings and other per-guest-pirq data.
>>>> * Protected by the domain's event-channel spinlock.
>>>> */
>>>> struct radix_tree_root pirq_tree;
>>>> unsigned int nr_pirqs;
>>>> +#endif
>>>
>>> Won't it be cleaner to just move this into arch_domain and avoid a
>>> bunch of the ifdefary? As the initialization of the fields would be
>>> moved to arch_domain_create() also.
>>
>> That's hard to decide without knowing what e.g. RISC-V is going to
>> want. Taking (past) IA-64 into consideration - that would likely
>> have wanted to select this new HAS_PIRQ, and hence keeping these
>> pieces where they are imo makes sense.
>
> I'm kind of confused, what does Arm do here? AFAICT the pirq_tree is
> used by both PV and HVM guests in order to store the native interrupt
> -> guest interrupt translation, doesn't Arm also need something
> similar?
According to [1] they don't, hence the (new in v2) change here. Aiui
they simply map IRQ to pIRQ 1:1.
Jan
[1] https://lists.xen.org/archives/html/xen-devel/2023-05/msg00258.html
|
