[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH] amd: disable C6 after 1000 days on Fam17h models 30-3fh
On 06.06.2023 14:47, Roger Pau Monné wrote: > On Mon, Jun 05, 2023 at 05:54:50PM +0200, Jan Beulich wrote: >> On 05.06.2023 17:10, Roger Pau Monne wrote: >>> As specified on Errata 1474: >>> >>> "A core will fail to exit CC6 after about 1044 days after the last >>> system reset. The time of failure may vary depending on the spread >>> spectrum and REFCLK frequency." >>> >>> Detect when running on AMD Fam17h models 30h-3fh and setup a timer to >>> prevent entering C6 after 1000 days have elapsed. Take into account >>> the TSC value at boot in order to account for any time elapsed before >>> Xen has been booted. >> >> Models 6x are also affected as per their RG. I have some trouble with >> the site, so it's too slow going to actually try and fish out the RGs >> for the other possible models. >> >> Given more than one set of models is affected I of course also wonder >> whether Hygon CPUs wouldn't be affected, too. But I realize we have >> hardly any means to find out. > > I've considered Hygon, but as you say I have no way I know to figure > out what models are affected. Well, see also Andrew's reply. >>> +static int __init cf_check amd_c6_errata(void) >>> +{ >>> + /* >>> + * Errata #1474: A Core May Hang After About 1044 Days >>> + * Set up a timer to disable C6 after 1000 days uptime. >>> + */ >>> + s_time_t; >>> + >>> + if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD || >>> + boot_cpu_data.x86 != 0x17 || >>> + (boot_cpu_data.x86_model & 0xf0) != 0x30) >> >> Perhaps better ... & ~0xf, just to be future-proof? > > Right, will need to change anyway to account for 0x60 models. But > x86_model is a char, and hence the mask is 0xff only (8 bits). I understand it is right now, hence why I said future proof. I consider it possible that upon widening the field an expression like the one above might be overlooked. >>> + return 0; >>> + >>> + /* >>> + * Deduct current TSC value, this would be relevant if >>> + * kexec'ed for example. >>> + */ >>> + delta = DAYS(1000) - tsc_ticks2ns(rdtsc()); >> >> Generally the TSC can be written (and we actually do so under certain >> circumstances), so deriving any absolute time from the TSC value is of >> at best questionable value. > > It's IMO better than not accounting for the TSC at all. Worst > case is we end up disabling C6 before actually required, but that > would leave us in safe position anyway. Hmm, yes, fair point. >>> + if (delta > 0) { >>> + static struct timer errata_c6; >>> + >>> + init_timer(&errata_c6, disable_c6, NULL, 0); >>> + set_timer(&errata_c6, NOW() + delta); >>> + } else >>> + disable_c6(NULL); >> >> The log message is going to be misleading in this case. Maybe pass >> that as the so far unused handler argument? Albeit I realize that this >> will mean casting away const-ness, which isn't very nice. > > I think we could use the same message in both cases, what about: > > "Disabling C6 after 1000 days hardware uptime due to AMD errata 1474" But that's still misleading if TSC was ever written. The message is pretty long already, but inserting "apparent" would address this. >>> --- a/xen/include/xen/time.h >>> +++ b/xen/include/xen/time.h >>> @@ -53,6 +53,7 @@ struct tm wallclock_time(uint64_t *ns); >>> >>> #define SYSTEM_TIME_HZ 1000000000ULL >>> #define NOW() ((s_time_t)get_s_time()) >>> +#define DAYS(_d) ((s_time_t)((_d) * 86400000000000ULL)) >>> #define SECONDS(_s) ((s_time_t)((_s) * 1000000000ULL)) >>> #define MILLISECS(_ms) ((s_time_t)((_ms) * 1000000ULL)) >>> #define MICROSECS(_us) ((s_time_t)((_us) * 1000ULL)) >> >> While consistent with the other macros we have here, I think this would >> be neater as >> >> #define DAYS(_d) SECONDS((_d) * 86400ULL)) > > Hm, it would make more sense to introduce the missing macros between > DAYS() and SECONDS() (MINUTES() and HOURS()) and use HOURS() in DAYS()? Probably, but I didn't want to go as far as asking for this. Jan
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