[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [XEN v8 5/5] xen/arm: p2m: Enable support for 32bit IPA for ARM_32
Hi Ayan, On 02/06/2023 13:07, Ayan Kumar Halder wrote: Refer ARM DDI 0406C.d ID040418, B3-1345, "A stage 2 translation with an input address range of 31-34 bits can start the translation either: - With a first-level lookup, accessing a first-level translation table with 2-16 entries. - With a second-level lookup, accessing a set of concatenated second-level translation tables" Thus, for 32 bit IPA, there will be no concatenated root level tables. So, the root-order is 0. Also, Refer ARM DDI 0406C.d ID040418, B3-1348 "Determining the required first lookup level for stage 2 translations For a stage 2 translation, the output address range from the stage 1 translations determines the required input address range for the stage 2 translation. The permitted values of VTCR.SL0 are: 0b00 Stage 2 translation lookup must start at the second level. 0b01 Stage 2 translation lookup must start at the first level. VTCR.T0SZ must indicate the required input address range. The size of the input address region is 2^(32-T0SZ) bytes." Thus VTCR.SL0 = 1 (maximum value) and VTCR.T0SZ = 0 when the size of input address region is 2^32 bytes. Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@xxxxxxx> Acked-by: Julien Grall <jgrall@xxxxxxxxxx> Cheers, -- Julien Grall
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