[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 2/3] x86: Introduce new debug.c for debug register infrastructure
- To: Jan Beulich <jbeulich@xxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Tue, 29 Aug 2023 15:25:39 +0100
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=N+wQ7Ben+xcbKUHXeLrwASrD+Z+XRv/FK5/PISgOCuY=; b=Mkom4c42+c3YzTPtjR+YC9Y3t+eUwXiJ5snvdtMrBN8CVqoyZrw7qTxCPie8uiEOrkMbKaPutUvZx+o5clg5lSR9339/Oy2Mx/3gnYoiiZ6IBZNaX8I9dJ2tkUAqTR+Wl5MCTZLD8fQjKSVC1kgPDFxWmTtyut5YSAIZgeMflzMRlgSR5B5mjl69AM9akHIV9XPOl21fgHZSQyqHgpszsEk4U+/lYYGZYdJY2TIhBjIw3nW0Fsj38Xq4LOJaxTIMnCvnd2HfSXuPxCvOj3YomHTX8SDerafiAXoJtF035KS5G87x3azdcTTM3vFFqS4OSHgju949lPVsJGEU/VQ9vw==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PtcYb6kdwkLXiP5T56E3bvXtQAQc9luX1/5zVG/02zXKhasdlf5sbLrRwFLa/nmZK89fsHSOMvKcMAJThrhDHa9fV/gY1aetLZh+tI79hnUqqVyN6U/ZCFcipI8osETdBvTUHHvwoDGyBlFsOl4ziLGQW3aMB9CTsPHXS5agOBGTGm1jXWO+cYHynVAYCwED84LFoTioW2JMycWxIYikVNFafuFKxF2siU69wYORyp7eGsDRzh9L4wcT1i9aWOXP/OQ4NV6t7SBraJ4ZoJUIaRrn5EFaUGoUye8WhJKqAdowEvSaqjB7aLb8u30fN3YUAQ4DNnZBp6CcRZaJG9SGdA==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com;
- Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Jinoh Kang <jinoh.kang.kr@xxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Tue, 29 Aug 2023 14:25:54 +0000
- Ironport-data: A9a23:Ba6N1qgZn975Nc2BmAYIqiNuX161pBEKZh0ujC45NGQN5FlHY01je htvX26Aa/aNYmvzKI0gati/9E4HuJXdzdVgTwBu/ChjEngb9cadCdqndUqhZCn6wu8v7q5Ex 55HNoSfdpBcolv0/ErF3m3J9CEkvU2wbuOgTrWCYmYpHlUMpB4J0XpLg/Q+jpNjne+3CgaMv cKai8DEMRqu1iUc3lg8sspvkzsx+qyo0N8klgZmP6sT7AWPzyB94K83fsldEVOpGuG4IcbiL wrz5OnR1n/U+R4rFuSknt7TGqHdauePVeQmoiM+t5mK2nCulARrukoIHKN0hXNsoyeIh7hMJ OBl7vRcf+uL0prkw4zxWzEAe8130DYvFLXveRBTuuTLp6HKnueFL1yDwyjaMKVBktubD12i+ tQ1eTsxQDq8qN7x/+yWF8t3lvYpPIr0adZ3VnFIlVk1DN4AaLWaGuDmwIEd2z09wMdTAfzZe swVLyJ1awjNaAFOPVFRD48imOCvhT/0dDgwRFC9/PJrpTSMilEuluGzYbI5efTTLSlRtm+eq njL4CLSBRYCOcbE4TGE7mitlqnEmiaTtIc6TefgpqM32APKroAVIBMXZ3H8m6C3sBCBHNZ8F HROqggIvLdnoSRHSfG4BXVUukWsvBQRRt5RGO0S8xyWx+zf5APxLncAZi5MbpohrsBebT4r0 FiJ2dDgAzMps6e9RneU97PSpjS3UQAFIGlHaSIaQA8t59j4vJp1nh/JVsxkEqO+kpvyAz6Y/ tyRhC03hrFWgctV0ay+pAnDm2j1+MmPSRMp7ALKWG7j9hl+eIOue42v7x7c8OpEK4GaCFKGu RDohvSj0QzHNrnV/ATlfQnHNOjBCyqtWNEEvWNSIg==
- Ironport-hdrordr: A9a23:VrIXuq+mAy93lsuwSyhuk+DYI+orL9Y04lQ7vn2ZKCYlFPBw8v rFoB11726XtN9zYhEdcLK7Scy9qBrnnPYfgLX5Vo3SODUO1lHYS72KLrGP/9QjIUDDHyJmup uIupIRNDVXYGIK7vrH3A==
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 29/08/2023 3:10 pm, Jan Beulich wrote:
> On 29.08.2023 15:43, Andrew Cooper wrote:
>> Broken out of the subsequent patch for clarity.
>>
>> Add stub x86_adj_dr{6,7}_rsvd() functions which will be extended in the
>> following patch to fix bugs, and adjust debugreg.h to compile with a more
>> minimal set of includes.
>>
>> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
> preferably with (nit) ...
>
>> --- a/xen/arch/x86/include/asm/debugreg.h
>> +++ b/xen/arch/x86/include/asm/debugreg.h
>> @@ -77,7 +77,18 @@
>> asm volatile ( "mov %%db" #reg ",%0" : "=r" (__val) ); \
>> __val; \
>> })
>> +
>> +struct vcpu;
>> long set_debugreg(struct vcpu *, unsigned int reg, unsigned long value);
>> void activate_debugregs(const struct vcpu *);
>>
>> +struct cpu_policy;
>> +
>> +/*
>> + * Architecturally dr6/7 are full GPR-width, but only the bottom 32 bits may
>> + * legally be non-zero. We avoid avoid storing the upper bits when
>> possible.
> ... one "avoid" dropped here.
Oops. Will fix.
Thanks.
~Andrew
|