[PATCH v10 38/38] x86/fred: Invoke FRED initialization code to enable FRED

[Xin Li <xin3.li@xxxxxxxxx>]

From: "H. Peter Anvin (Intel)" <hpa@xxxxxxxxx>

Let cpu_init_exception_handling() call cpu_init_fred_exceptions() to
initialize FRED. However if FRED is unavailable or disabled, it falls
back to set up TSS IST and initialize IDT.

Signed-off-by: H. Peter Anvin (Intel) <hpa@xxxxxxxxx>
Co-developed-by: Xin Li <xin3.li@xxxxxxxxx>
Tested-by: Shan Kang <shan.kang@xxxxxxxxx>
Signed-off-by: Xin Li <xin3.li@xxxxxxxxx>
---

Changes since v8:
* Move this patch after all required changes are in place (Thomas
  Gleixner).
---
 arch/x86/kernel/cpu/common.c | 17 ++++++++++++-----
 arch/x86/kernel/irqinit.c    |  7 ++++++-
 arch/x86/kernel/traps.c      |  5 ++++-
 3 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 4cb36e241c9a..e230d3f4c556 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -61,6 +61,7 @@
 #include <asm/microcode.h>
 #include <asm/intel-family.h>
 #include <asm/cpu_device_id.h>
+#include <asm/fred.h>
 #include <asm/uv/uv.h>
 #include <asm/set_memory.h>
 #include <asm/traps.h>
@@ -2128,7 +2129,10 @@ void syscall_init(void)
        /* The default user and kernel segments */
        wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
 
-       idt_syscall_init();
+       if (cpu_feature_enabled(X86_FEATURE_FRED))
+               fred_syscall_init();
+       else
+               idt_syscall_init();
 }
 
 #else  /* CONFIG_X86_64 */
@@ -2244,8 +2248,9 @@ void cpu_init_exception_handling(void)
        /* paranoid_entry() gets the CPU number from the GDT */
        setup_getcpu(cpu);
 
-       /* IST vectors need TSS to be set up. */
-       tss_setup_ist(tss);
+       /* For IDT mode, IST vectors need to be set in TSS. */
+       if (!cpu_feature_enabled(X86_FEATURE_FRED))
+               tss_setup_ist(tss);
        tss_setup_io_bitmap(tss);
        set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
 
@@ -2254,8 +2259,10 @@ void cpu_init_exception_handling(void)
        /* GHCB needs to be setup to handle #VC. */
        setup_ghcb();
 
-       /* Finally load the IDT */
-       load_current_idt();
+       if (cpu_feature_enabled(X86_FEATURE_FRED))
+               cpu_init_fred_exceptions();
+       else
+               load_current_idt();
 }
 
 /*
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index c683666876f1..f79c5edc0b89 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -28,6 +28,7 @@
 #include <asm/setup.h>
 #include <asm/i8259.h>
 #include <asm/traps.h>
+#include <asm/fred.h>
 #include <asm/prom.h>
 
 /*
@@ -96,7 +97,11 @@ void __init native_init_IRQ(void)
        /* Execute any quirks before the call gates are initialised: */
        x86_init.irqs.pre_vector_init();
 
-       idt_setup_apic_and_irq_gates();
+       if (cpu_feature_enabled(X86_FEATURE_FRED))
+               fred_complete_exception_setup();
+       else
+               idt_setup_apic_and_irq_gates();
+
        lapic_assign_system_vectors();
 
        if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs()) {
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 848c85208a57..0ee78a30e14a 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -1411,7 +1411,10 @@ void __init trap_init(void)
 
        /* Initialize TSS before setting up traps so ISTs work */
        cpu_init_exception_handling();
+
        /* Setup traps as cpu_init() might #GP */
-       idt_setup_traps();
+       if (!cpu_feature_enabled(X86_FEATURE_FRED))
+               idt_setup_traps();
+
        cpu_init();
 }
-- 
2.34.1