[PATCH v10 20/38] x86/fred: Disallow the swapgs instruction when FRED is enabled

[Xin Li <xin3.li@xxxxxxxxx>]

From: "H. Peter Anvin (Intel)" <hpa@xxxxxxxxx>

SWAPGS is no longer needed thus NOT allowed with FRED because FRED
transitions ensure that an operating system can _always_ operate
with its own GS base address:
- For events that occur in ring 3, FRED event delivery swaps the GS
  base address with the IA32_KERNEL_GS_BASE MSR.
- ERETU (the FRED transition that returns to ring 3) also swaps the
  GS base address with the IA32_KERNEL_GS_BASE MSR.

And the operating system can still setup the GS segment for a user
thread without the need of loading a user thread GS with:
- Using LKGS, available with FRED, to modify other attributes of the
  GS segment without compromising its ability always to operate with
  its own GS base address.
- Accessing the GS segment base address for a user thread as before
  using RDMSR or WRMSR on the IA32_KERNEL_GS_BASE MSR.

Note, LKGS loads the GS base address into the IA32_KERNEL_GS_BASE MSR
instead of the GS segment’s descriptor cache. As such, the operating
system never changes its runtime GS base address.

Signed-off-by: H. Peter Anvin (Intel) <hpa@xxxxxxxxx>
Tested-by: Shan Kang <shan.kang@xxxxxxxxx>
Signed-off-by: Xin Li <xin3.li@xxxxxxxxx>
---

Changes since v8:
* Explain why writing directly to the IA32_KERNEL_GS_BASE MSR is
  doing the right thing (Thomas Gleixner).
---
 arch/x86/kernel/process_64.c | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 0f78b58021bb..4f87f5987ae8 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -166,7 +166,29 @@ static noinstr unsigned long __rdgsbase_inactive(void)
 
        lockdep_assert_irqs_disabled();
 
-       if (!cpu_feature_enabled(X86_FEATURE_XENPV)) {
+       /*
+        * SWAPGS is no longer needed thus NOT allowed with FRED because
+        * FRED transitions ensure that an operating system can _always_
+        * operate with its own GS base address:
+        * - For events that occur in ring 3, FRED event delivery swaps
+        *   the GS base address with the IA32_KERNEL_GS_BASE MSR.
+        * - ERETU (the FRED transition that returns to ring 3) also swaps
+        *   the GS base address with the IA32_KERNEL_GS_BASE MSR.
+        *
+        * And the operating system can still setup the GS segment for a
+        * user thread without the need of loading a user thread GS with:
+        * - Using LKGS, available with FRED, to modify other attributes
+        *   of the GS segment without compromising its ability always to
+        *   operate with its own GS base address.
+        * - Accessing the GS segment base address for a user thread as
+        *   before using RDMSR or WRMSR on the IA32_KERNEL_GS_BASE MSR.
+        *
+        * Note, LKGS loads the GS base address into the IA32_KERNEL_GS_BASE
+        * MSR instead of the GS segment’s descriptor cache. As such, the
+        * operating system never changes its runtime GS base address.
+        */
+       if (!cpu_feature_enabled(X86_FEATURE_FRED) &&
+           !cpu_feature_enabled(X86_FEATURE_XENPV)) {
                native_swapgs();
                gsbase = rdgsbase();
                native_swapgs();
@@ -191,7 +213,8 @@ static noinstr void __wrgsbase_inactive(unsigned long 
gsbase)
 {
        lockdep_assert_irqs_disabled();
 
-       if (!cpu_feature_enabled(X86_FEATURE_XENPV)) {
+       if (!cpu_feature_enabled(X86_FEATURE_FRED) &&
+           !cpu_feature_enabled(X86_FEATURE_XENPV)) {
                native_swapgs();
                wrgsbase(gsbase);
                native_swapgs();
-- 
2.34.1