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Re: [PATCH 5/7] x86: Introduce x86_merge_dr6()
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Mon, 25 Sep 2023 09:30:22 +0200
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- Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Jinoh Kang <jinoh.kang.kr@xxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Mon, 25 Sep 2023 07:30:40 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 22.09.2023 18:11, Andrew Cooper wrote:
> On 18/09/2023 12:37 pm, Jan Beulich wrote:
>> On 15.09.2023 22:36, Andrew Cooper wrote:
>>> The current logic used to update %dr6 when injecting #DB is buggy.
>>>
>>> The SDM/APM documention on %dr6 updates is far from ideal, but does at least
>>> make clear that it's non-trivial. The actual behaviour is to overwrite
>>> B{0..3} and accumulate all other bits.
>> As mentioned before, I'm okay to ack this patch provided it is explicitly
>> said
>> where the information is coming from.
>
> The information *is* coming from the relevant paragraph of the relevant
> chapters of the relevant manuals.
>
> I don't need to teach programmers how to suck eggs. Nor am I going to
> quote buggy manuals (corrections are pending for both) as a
> justification for restating several paragraphs of information as a oneliner.
Earlier on you said this to my original request:
'SDM Vol3 18.2.3 Debug Status Register (DR6) says
"Certain debug exceptions may clear bits 0-3. The remaining contents of
the DR6 register are never cleared by the processor."'
"Certain" and "may" do not describe the behavior that your change implements.
Hence imo there's still a need to clarify where the extra information is
coming from. Pending corrections are of course appreciated; in case you have
been told the new wording already, perhaps you could quote that?
Jan
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