[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [for-4.18][PATCH v2] x86/amd: Address AMD erratum #1485



Hi,

On Fri, Oct 13, 2023 at 03:41:49PM +0100, Julien Grall wrote:
> Hi Alejandro,
> 
> The original e-mail didn't yet reach my inbox. So answering here as there
> are enough context.
> 
> On 13/10/2023 15:33, Alejandro Vallejo wrote:
> > On Fri, Oct 13, 2023 at 09:40:52PM +0800, Andrew Cooper wrote:
> > > On 13/10/2023 9:18 pm, Alejandro Vallejo wrote:
> > > > diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
> > > > index 4f27187f92..085c4772d7 100644
> > > > --- a/xen/arch/x86/cpu/amd.c
> > > > +++ b/xen/arch/x86/cpu/amd.c
> > > > @@ -1167,6 +1167,14 @@ static void cf_check init_amd(struct cpuinfo_x86 
> > > > *c)
> > > >         if (c->x86 == 0x10)
> > > >                 __clear_bit(X86_FEATURE_MONITOR, c->x86_capability);
> > > > +       /* Fix for AMD erratum #1485 */
> > > > +       if (!cpu_has_hypervisor && c->x86 == 0x19 && is_zen4_uarch()) {
> > > > +               rdmsrl(MSR_AMD64_BP_CFG, value);
> > > > +               #define ZEN4_BP_CFG_SHARED_BTB_FIX (1ull << 5)
> 
> You are introducing a violation to MISRA Rule 7.3 [1] which was accepted
> recently. You want to use 1ULL rather than the lower case version.
> 
> [1] 
> https://gitlab.com/MISRA/MISRA-C/MISRA-C-2012/Example-Suite/-/blob/master/R_07_03.c
> 
> Cheers,
> 
> -- 
> Julien Grall
Oh, I didn't know about that one. Fair enough.

Thanks,
Alejandro



 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.