[RFC PATCH 09/22] x86/PMUv1: consistently use 8 perf counters in Dom0

[Edwin Török <edwin.torok@xxxxxxxxx>]

From: Edwin Török <edvin.torok@xxxxxxxxxx>

The code is currently inconsistent: supports 4 on read and 8 on write.
Sandy Bridge+ supports 8 of these, and the MSR range is architecturally
reserved, so always support 8.

Make it a macro to ensure we use the same value everywhere.

Although DomUs are now restricted to only 4 PMCs, we may still want to
use all 8 in Dom0 when available, and since the default rdwmsr
restrictions Dom0 would be prevented to read these MSRs as well.

Depends on:
"x86/PMUv1: limit arch PMCs to 4 for non-Dom0"

Backport: 4.15+

Signed-off-by: Edwin Török <edvin.torok@xxxxxxxxxx>
---
 xen/arch/x86/hvm/vmx/vmx.c           | 8 ++++----
 xen/arch/x86/include/asm/msr-index.h | 3 +++
 xen/arch/x86/pv/emul-priv-op.c       | 8 ++++----
 3 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index f6e5123f66..7d51addf7a 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -3360,8 +3360,8 @@ static int cf_check vmx_msr_read_intercept(
                        MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
         /* Perhaps vpmu will change some bits. */
         /* FALLTHROUGH */
-    case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7):
-    case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(3):
+    case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR_LAST:
+    case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL_LAST:
     case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2:
     case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL:
     case MSR_IA32_PEBS_ENABLE:
@@ -3678,8 +3678,8 @@ static int cf_check vmx_msr_write_intercept(
             goto gp_fault;
         break;
 
-    case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7):
-    case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(7):
+    case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR_LAST:
+    case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL_LAST:
     case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2:
     case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL:
     case MSR_IA32_PEBS_ENABLE:
diff --git a/xen/arch/x86/include/asm/msr-index.h 
b/xen/arch/x86/include/asm/msr-index.h
index 8601f8f426..011a926e0e 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -521,8 +521,11 @@
 #define MSR_IA32_PSR_MBA_MASK(n)       (0x00000d50 + (n))
 
 /* Intel Model 6 */
+#define MSR_P6_PERFCTR_MAX             8
 #define MSR_P6_PERFCTR(n)              (0x000000c1 + (n))
 #define MSR_P6_EVNTSEL(n)              (0x00000186 + (n))
+#define MSR_P6_PERFCTR_LAST            MSR_P6_PERFCTR(MSR_P6_PERFCTR_MAX-1)
+#define MSR_P6_EVNTSEL_LAST            MSR_P6_EVNTSEL(MSR_P6_PERFCTR_MAX-1)
 
 /* P4/Xeon+ specific */
 #define MSR_IA32_MCG_EAX               0x00000180
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 978ae679a2..301a70f5ea 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -965,8 +965,8 @@ static int cf_check read_msr(
         *val = 0;
         return X86EMUL_OKAY;
 
-    case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR(7):
-    case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3):
+    case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR_LAST:
+    case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST:
     case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2:
     case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL:
         if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
@@ -1145,8 +1145,8 @@ static int cf_check write_msr(
             return X86EMUL_OKAY;
         break;
 
-    case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR(7):
-    case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3):
+    case MSR_P6_PERFCTR(0) ... MSR_P6_PERFCTR_LAST:
+    case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL_LAST:
     case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2:
     case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL:
         if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
-- 
2.41.0