Re: [RFC PATCH 12/22] x86/msr-index: define more architectural MSRs

[Jan Beulich <jbeulich@xxxxxxxx>]

On 25.10.2023 21:29, Edwin Török wrote:
> From: Edwin Török <edvin.torok@xxxxxxxxxx>
> 
> Add most architectural MSRs, except those behind CPUID features that are
> not yet implemented, such as TME, SGX.

I'm not convinced we should blindly add MSR definitions for ones we
don't use. But if you do, ...

> --- a/xen/arch/x86/include/asm/msr-index.h
> +++ b/xen/arch/x86/include/asm/msr-index.h
> @@ -58,6 +58,14 @@
>  #define  PRED_CMD_IBPB                      (_AC(1, ULL) <<  0)
>  #define  PRED_CMD_SBPB                      (_AC(1, ULL) <<  7)
>  
> +#define MSR_IA32_SMM_MONITOR_CTL            0x0000009b
> +#define MSR_IA32_SMBASE                     0x0000009e
> +#define MSR_IA32_SMRR_PHYSBASE              0x000001f2
> +#define MSR_IA32_SMRR_PHYSMASK              0x000001f3
> +#define MSR_IA32_PLATFORM_DCA_CAP           0x000001f8
> +#define MSR_IA32_CPU_DCA_CAP                0x000001f9
> +#define MSR_IA32_DCA_0_CAP                  0x000001fa
> +
>  #define MSR_PPIN_CTL                        0x0000004e
>  #define  PPIN_LOCKOUT                       (_AC(1, ULL) <<  0)
>  #define  PPIN_ENABLE                        (_AC(1, ULL) <<  1)
> @@ -267,13 +275,21 @@
>  #define MSR_IA32_MCG_CAP             0x00000179
>  #define MSR_IA32_MCG_STATUS          0x0000017a
>  #define MSR_IA32_MCG_CTL             0x0000017b
> -#define MSR_IA32_MCG_EXT_CTL 0x000004d0
> +#define MSR_IA32_MCG_EXT_CTL         0x000004d0

... please obey to the comment a few lines up from here: Altering
indentation is kind of okay, but most of what you add below here
should be added (well-formed) above that comment.

Jan

>  #define MSR_IA32_PEBS_ENABLE         0x000003f1
>  #define MSR_IA32_DS_AREA             0x00000600
>  #define MSR_IA32_PERF_CAPABILITIES   0x00000345
>  /* Lower 6 bits define the format of the address in the LBR stack */
> -#define MSR_IA32_PERF_CAP_LBR_FORMAT 0x3f
> +#define MSR_IA32_PERF_CAP_LBR_FORMAT         0x3f
> +#define MSR_IA32_PERF_CAP_PEBS_TRAP          (_AC(1,ULL) << 6)
> +#define MSR_IA32_PERF_CAP_PEBS_SAVE_ARCH_REGS        (_AC(1,ULL) << 7)
> +#define MSR_IA32_PERF_CAP_PEBS_RECORD_FORMAT 0xf00
> +#define MSR_IA32_PERF_CAP_FREEZE_WHILE_SMM   (_AC(1,ULL) << 12)
> +#define MSR_IA32_PERF_CAP_FULLWIDTH_PMC      (_AC(1,ULL) << 13)
> +#define MSR_IA32_PERF_CAP_PEBS_BASELINE              (_AC(1,ULL) << 14)
> +#define MSR_IA32_PERF_CAP_PERF_METRICS               (_AC(1,ULL) << 15)
> +#define MSR_IA32_PERF_CAP_PEBS_TO_PT         (_AC(1,ULL) << 16)
>  
>  #define MSR_IA32_BNDCFGS             0x00000d90
>  #define IA32_BNDCFGS_ENABLE          0x00000001
> @@ -307,6 +323,8 @@
>  #define IA32_DEBUGCTLMSR_BTS_OFF_USR (1<<10) /* BTS off if CPL > 0 */
>  #define IA32_DEBUGCTLMSR_FREEZE_LBRS_ON_PMI  (1<<11) /* LBR stack frozen on 
> PMI */
>  #define IA32_DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI       (1<<12) /*  Global 
> counter control ENABLE bit frozen on PMI */
> +#define IA32_DEBUGCTLMSR_ENABLE_UNCORE_PMI   (1<<13) /* Enable uncore PMI */
> +#define IA32_DEBUGCTLMSR_FREEZE_WHILE_SMM    (1<<14) /* Freeze perfmon/trace 
> while in SMM */
>  #define IA32_DEBUGCTLMSR_RTM                 (1<<15) /* RTM debugging enable 
> */
>  
>  #define MSR_IA32_LASTBRANCHFROMIP    0x000001db
> @@ -469,6 +487,7 @@
>  #define MSR_VIA_RNG                  0x0000110b
>  
>  /* Intel defined MSRs. */
> +#define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
>  #define MSR_IA32_TSC                 0x00000010
>  #define MSR_IA32_PLATFORM_ID         0x00000017
>  #define MSR_IA32_EBL_CR_POWERON              0x0000002a
> @@ -491,6 +510,7 @@
>  #define MSR_IA32_PERF_STATUS         0x00000198
>  #define MSR_IA32_PERF_CTL            0x00000199
>  
> +#define MSR_IA32_UMWAIT_CONTROL              0x000000e1
>  #define MSR_IA32_MPERF                       0x000000e7
>  #define MSR_IA32_APERF                       0x000000e8
>  
> @@ -498,6 +518,7 @@
>  #define MSR_IA32_THERM_INTERRUPT     0x0000019b
>  #define MSR_IA32_THERM_STATUS                0x0000019c
>  #define MSR_IA32_MISC_ENABLE         0x000001a0
> +#define MSR_IA32_MISC_ENABLE_FAST_STRINGS (1<<0)
>  #define MSR_IA32_MISC_ENABLE_PERF_AVAIL   (1<<7)
>  #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL  (1<<11)
>  #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
> @@ -508,15 +529,38 @@
>  #define MSR_IA32_MISC_ENABLE_TURBO_DISENGAGE (_AC(1, ULL) << 38)
>  
>  #define MSR_IA32_TSC_DEADLINE                0x000006E0
> +
> +#define MSR_IA32_PM_ENABLE           0x00000770
> +#define MSR_IA32_HWP_CAPABILITIES    0x00000771
> +#define MSR_IA32_HWP_REQUEST_PKG     0x00000772
> +#define MSR_IA32_HWP_INTERRUPT               0x00000773
> +#define MSR_IA32_HWP_REQUEST         0x00000774
> +#define MSR_IA32_PECI_HWP_REQUEST_INFO       0x00000775
> +#define MSR_IA32_HWP_STATUS          0x00000777
> +
> +#define MSR_IA32_PKG_HDC_CTL         0x00000db0
> +#define MSR_IA32_PM_CTL1             0x00000db1
> +#define MSR_IA32_THREAD_STALL                0x00000db2
> +#define MSR_IA32_HW_FEEDBACK_PTR     0x000017d0
> +#define MSR_IA32_HW_FEEDBACK_CONFIG  0x000017d1
> +
> +#define MSR_TEMPERATURE_TARGET               0x000001a2
> +#define MSR_TURBO_RATIO_LIMIT                0x000001ad
> +#define MSR_TURBO_RATIO_LIMIT1               0x000001ae
> +#define MSR_TURBO_RATIO_LIMIT2               0x000001af
> +
>  #define MSR_IA32_ENERGY_PERF_BIAS    0x000001b0
> +#define MSR_IA32_PACKAGE_THERM_STATUS        0x000001b1
> +#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
>  
>  /* Platform Shared Resource MSRs */
> +#define MSR_IA32_PSR_L3_QOS_CFG              0x00000c81
> +#define MSR_IA32_PSR_L2_QOS_CFG              0x00000c82
>  #define MSR_IA32_CMT_EVTSEL          0x00000c8d
>  #define MSR_IA32_CMT_EVTSEL_UE_MASK  0x0000ffff
>  #define MSR_IA32_CMT_CTR             0x00000c8e
>  #define MSR_IA32_PSR_ASSOC           0x00000c8f
> -#define MSR_IA32_PSR_L3_QOS_CFG      0x00000c81
> -#define MSR_IA32_PSR_L3_MASK(n)      (0x00000c90 + (n))
> +#define MSR_IA32_PSR_L3_MASK(n)              (0x00000c90 + (n))
>  #define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1)
>  #define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2)
>  #define MSR_IA32_PSR_L2_MASK(n)              (0x00000d10 + (n))
> @@ -682,6 +726,8 @@
>  #define MSR_CORE_PERF_GLOBAL_STATUS  0x0000038e
>  #define MSR_CORE_PERF_GLOBAL_CTRL    0x0000038f
>  #define MSR_CORE_PERF_GLOBAL_OVF_CTRL        0x00000390
> +#define MSR_CORE_PERF_GLOBAL_STATUS_SET      0x00000391
> +#define MSR_CORE_PERF_GLOBAL_INUSE   0x00000392
>  
>  /* Intel cpuid spoofing MSRs */
>  #define MSR_INTEL_MASK_V1_CPUID1        0x00000478