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Re: [PATCH] x86/kexec: Separate code and data by at least 1 cacheline
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Wed, 2 Oct 2024 14:08:08 +0200
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- Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Wed, 02 Oct 2024 12:08:28 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 02.10.2024 12:30, Andrew Cooper wrote:
> No functional change, but it performs a bit better.
>
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
A question nevertheless:
> --- a/xen/arch/x86/x86_64/kexec_reloc.S
> +++ b/xen/arch/x86/x86_64/kexec_reloc.S
> @@ -19,6 +19,7 @@
> #include <xen/kimage.h>
>
> #include <asm/asm_defns.h>
> +#include <asm/cache.h>
> #include <asm/msr-index.h>
> #include <asm/page.h>
> #include <asm/machine_kexec.h>
> @@ -174,6 +175,9 @@ FUNC_LOCAL(compatibility_mode)
> ud2
> END(compatibility_mode)
>
> + /* Separate code and data into into different cache lines */
> + .balign L1_CACHE_BYTES
> +
> DATA_LOCAL(compat_mode_gdt_desc, 4)
> .word .Lcompat_mode_gdt_end - compat_mode_gdt -1
> .quad 0x0000000000000000 /* set in call_32_bit above */
Because of L1_CACHE_BYTES being 128, you indeed put at least 1 cache line in
between. Is that necessary, though? Just starting data on the next cache line
ought to be enough? IOW if and when we adjust L1_CACHE_BYTES, we won't need
to touch this again, just that the title here then would end up slightly
misleading.
Jan
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