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Re: [PATCH v2 07/10] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow eSPI processing
- To: Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- From: Leonid Komarianskyi <Leonid_Komarianskyi@xxxxxxxx>
- Date: Fri, 22 Aug 2025 06:56:08 +0000
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- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>
- Delivery-date: Fri, 22 Aug 2025 06:56:21 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Thread-index: AQHcB5d8lU0HcDjyxEOVNNx+lAhf97RuVHuA
- Thread-topic: [PATCH v2 07/10] xen/arm: gicv3: modify ICH_LR_PHYSICAL_MASK to allow eSPI processing
Hi Volodymyr,
On 21.08.25 19:27, Volodymyr Babchuk wrote:
> Hi Leonid,
>
>
> Leonid Komarianskyi <Leonid_Komarianskyi@xxxxxxxx> writes:
>
>> To properly deactivate guest interrupts and allow them to be retriggered
>> after the initial trigger, the LR needs to be updated. The current
>> implementation ignores interrupts outside the range specified by the mask
>> 0x3FF, which only covers IRQ numbers up to 1023. To enable processing of
>> eSPI interrupts, this patch updates the mask to 0x13FF.
>
> I am not sure how this supposed to work. According to the arch
> specification, pINTID field in ICH_LR<n>_EL2 is only 12 bits wide.
>
>
Thank you for your review.
According to the specification, the pINTID field in ICH_LR<n>_EL2 is 13
bits wide ([44:32] bits):
> A hardware physical identifier is only required in List Registers for
> interrupts that require deactivation. This means only 13 bits of
> Physical INTID are required, regardless of the number specified by
> ICC_CTLR_EL1.IDbits.
0x13FF is a 13-bit number that fits into the corresponding register
field and covers the maximum eSPI INTID value - 5119.
Best regards,
Leonid
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