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Re: [PATCH 1/6] x86/vpmu: Expose up to 8 Intel event selectors in PV Dom0
- To: Teddy Astie <teddy.astie@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Tue, 24 Mar 2026 09:55:02 +0100
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- Delivery-date: Tue, 24 Mar 2026 08:55:10 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 10.03.2026 17:44, Teddy Astie wrote:
> Most (if not all) Intel CPUs starting from Sandy Bridge have up to 8
> event selectors per core, which could be halved per hyperthread.
>
> However, current PV emulation logic doesn't support up to 8 event selector,
> leading to errors when trying to access them, hence, preventing Linux from
> driving the vPMU correctly.
>
> Make sure up to MSR_P6_EVNTSEL(7) is usable, which is the same upper bound as
> used in VMX code.
>
> The check if the event selector actually exist for the hardware is done in
> core2_vpmu_do_{rdmsr,wrmsr}, hence we're not allowing to access non-existent
> MSRs.
>
> Fixes: 27c554198666 ("x86/VPMU: add support for PMU register handling on PV
> guests")
> Signed-off-by: Teddy Astie <teddy.astie@xxxxxxxxxx>
Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
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