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Re: [PATCH 2/6] x86/vpmu: Expose PEBS and DS area in PV mode
- To: Teddy Astie <teddy.astie@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Tue, 24 Mar 2026 10:11:23 +0100
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- Delivery-date: Tue, 24 Mar 2026 09:11:41 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 10.03.2026 17:44, Teddy Astie wrote:
> I don't see any reason for them for not be available, especially
> since core2_vpmu_do_wrmsr has PV specific logic for MSR_IA32_DS_AREA.
This is really dangerous: You allow PV domains to control whether the area
is actually mapped. It lacking a mapping can, iirc, on at least some CPUs
result in a complete hang. I do, in fact, have been carrying a patch to
completely disallow DS area use for PV, eliminating the misleading code
you refer to.
Also note that VPMU_CPU_HAS_DS cannot be set for PV vCPU-s anyway.
> Fixes: 27c554198666 ("x86/VPMU: add support for PMU register handling on PV
> guests")
Not just because of the above, I'm pretty sure a Fixes: tag is inappropriate
here.
Jan
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